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Features
* Clock Controller
- 80C51 core with 6 clocks per instruction - 8 MHz On-Chip Oscillator - PLL for generating clock to supply CPU core, USB and Smart Card Interfaces - Programmable CPU clock from 500 KHz / X1 to 48 MHz / X1 Reset Controller - Power On Reset (POR) feature avoiding an external reset capacitor - Power Fail Detector (PFD) - Watch-Dog Timer Power Management - Two power saving modes : Idle and Power Down - Four Power Down Wake-up Sources : Smart Card Detection, Keyboard Interrupt, USB Resume, External Interrupt - Input Voltage Range : 3.6V - 5.5V - Core's Power Consumption (Without Smart Card and USB) : *30 mA Maximum Operating Current @ 48 MHz / X1 *200 A Maximum Power-down Current @ 5.5V Interrupt Controller - up to 9 interrupt sources - up to 4 Level Priority Memory Controller - Internal Program memory : *up to 32KB of Flash or CRAM or ROM for AT8xC5122 *up to 30KB of ROM for AT83C5123 - Internal Data Memory : 768 bytes including 256 bytes of data and 512 bytes of XRAM - Optional : internal data E2PROM 512 bytes Two 16-bit Timer/Counters USB 2.0 Full Speed Interface - 48 MHz DPLL - On-Chip 3.3V USB voltage regulator and transceivers - Software detach feature - 7 endpoints programmable with In or out directions and ISO, Bulk or Interrupt Transfers : *Endpoint 0: 32 Bytes Bidirectionnal FIFO for Control transfers *Endpoints 1,2,3: 8 bytes FIFO *Endpoints 4,5: 64 Bytes FIFO *Endpoint 6: 2*64 bytes FIFO with Pin-Pong feature ISO 7816 UART Interface Fully Compliant with EMV, GIE-CB and WHQL Standards - Programmable ISO clock from 1 MHz to 4.8 MHz - Card insertion/removal detection with automatic deactivation sequence - Programmable Baud Rate Generator from 372 to 11.625 clock pulses - Synchronous/Asynchronous Protocols T=0 and T=1 with Direct or Inverse Convention - Automatic character repetition on parity errors - 32 Bit Waiting Time Counter - 16 Bit Guard Time Counter - Internal Step Up/Down Converter with Programmable Voltage Output : *1.8V-30 mA, 3V-60 mA and 5V-60 mA - Current overload protection - 6 kV ESD (MIL/STD 833 Class 3) protection on whole Smart Card Interface Alternate Smart Card Interface with CLK, IO and RST UART Interface with Integrated Baud Rate Generator (BRG) Keyboard interface with up to 20x8 matrix management capability Master/Slave SPI Interface Four 8 bit Ports, one 6 bit port, one 3-bit port - Up to Seven LED outputs with 3 level programmable current source : 2, 4 and 10 mA - Two General Purpose I/O programmable as external interrupts - Up to 8 input lines programmable as interrupts - Up to 30 output lines
*
*
* *
C51 Microcontroller with USB and Smart Card Reader Interfaces AT83C5122 AT83EC5122 AT85C5122 AT89C5122 AT89C5122DS AT83C5123 AT83EC5123
* *
*
* * * * *
Rev. 4202D-SCR-06/05
1
Reference Documents
The user must get the following additionnal documents which are not included but which complete this product datasheet * * Product Errata Sheet Bootloader Datasheet
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AT8xC5122/23
4202D-SCR-06/05
AT8xC5122/23
Product Description
AT8xC5122/23 products are high-performance CMOS derivatives of the 80C51 8-bit microcontrollers designed for USB smart card reader applications. The AT8xC5122 is proposed in four versions : - ROM version with or without internal data E2PROM. The ROM device is only factory programmable. - CRAM version without internal data E2PROM. The CRAM device implements a volatile program memory which is programmed by means of an embedded ROMed bootloader which transfers the code from a remote software programming tool called FLIP through UART or USB interfaces. - Flash version without internal data E2PROM. At power-up, the program located in the flash memory is transferred into the CRAM then executed. The AT83C5123 is a low pin count of the AT8xC5122 and is proposed in ROM version with or without internal data E2PROM. The ROM device is only factory programmable. The AT8xC5122DS is a secure version of the AT8xC5122 on which the external program memory access mode is disabled.
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4202D-SCR-06/05
Table 1. Product versions
Features AT83C5122 VQFP64 Packages QFN64 PLCC28 Die Form Program memory Internal Data E2PROM Embedded bootloader 32KB ROM No No 30KB ROM 512 Bytes No VQFP64 PLCC28 AT83EC5122 AT85C5122 PLCC68 VQFP64 PLCC28 Die Form 32KB CRAM No Yes AT89C5122 VQFP64 QFN64 PLCC28 32KB E2PROM No Yes AT89C5122DS AT83C5123 VQFP32 VQFP64 QFN64 QFN32 PLCC28 Die Form 32KB E2PROM No Yes 30KB ROM No No AT83EC5123 QFN32 VQFP32 PLCC28
30KB ROM 512 Bytes No
Features not available : - Keyboard Interface VQFP32, QFN32 packages - Master/Slave SPI Interface - External Program Memory Access Reduced features : - Only 12 I/O with up to 4 LED Outputs with Programmable Current Features PLCC68, VQFP64,QFN64 packages All features are available except External Program Memory Access Features not available : - Alternate Smart Card Interface - Keyboard Interface PLCC28 package - Master/Slave SPI Interface - External Program Memory Access Reduced features : - Only 7 I/O with up to 4 LED Outputs with Programmable Current
All features are available
Note:
The PLCC28 pinout is common to AT8xC5122 and AT83C5123 products
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AT8xC5122/23
4202D-SCR-06/05
AT8xC5122/23
AT8xC5122 Block Diagram
VSS VCC
INT[0-1]
CCLK1
CRST1
T[0-1]
3.3 V Regulator
XTAL1 XTAL2
8 MHz Oscillator
256 x 8 RAM 80C518-BIT CORE
256 x 8 RAM
512 x 8 XRAM
UART Interf ace
16-BIT TIMERS
Interrupt Controller
Alternate Card
DC/DC Conv erter ISO 7816 Interface
CVSS
CVCC
CIO1
RxD
TxD
L I
CPRES CRST CCLK CIO CC4 CC8
PLLF
PLL
INTERNALADDRESSAND DATABUS
RST
WATCH-DOG POR PFD RESET
32K x 8 ROM (1)
32K x 8 CRAM (1)
32K x 8 E2PROM(1) 512 x 8 E2PROM(1)
SPI Interf ace
ExternalMemory Controller
USB Interf ace
3.3V Regulator
MISO
ALE
AD[0-7]
MOSI
SS
SCK
PSEN
A[8-15]
WR
R D
D+
D-
VREF
AVCC
ParallelI/OPorts 8-BIT PORT 3-BIT PORT 8-BIT PORT 8-BIT PORT 6-BIT PORT 8-BIT PORT LED's KBD Interf ace
Note 1 : the implementation of these f eatures depends on product v ersions
P1[2,6-7]
LED[0-6]
P0[0-7]
P2[0-7]
P3[0-7]
P4[0-5]
P5[0-7]
AT83C5123 Block Diagram
VSS VCC
KB[0-7]
INT[0-1]
CCLK1
CRST1
T[0-1]
3.3 V Regulator
XTAL1 XTAL2
8 MHz Oscillator
256 x 8 RAM 80C518-BIT CORE
256 x 8 RAM
512 x 8 XRAM
UART Interf ace
16-BIT TIMERS
Interrupt Controller
Alternate Card
DC/DC Conv erter ISO 7816 Interface
CVSS
CVCC
CIO1
RxD
TxD
L I
AVSS
DVCC
EA
CPRES CRST CCLK CIO CC4 CC8
PLLF
PLL
INTERNALADDRESSAND DATABUS
RST
WATCH-DOG POR PFD RESET
30K x 8 ROM
512 x 8 E2PROM(1)
USB Interf ace
3.3V Regulator
D+
D-
VREF
AVCC
3-BIT PORT
8-BIT PORT
1-BIT PORT
LED's
Note 1 : the implementation of these f eatures depends on product v ersions
P1[2,6-7]
LED[0-3]
P3[0-7]
P5.0
AVSS
DVCC
ParallelI/OPorts
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4202D-SCR-06/05
Pinout
High Pin Count Package Description
AT8xC5122 version Figure 1. VQFP64 Package Pinout
P1.7/CCLK1 VREF
P2.2/A10
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES CC8 P5.7/KB7 P5.6/KB6 CRST P5.5/KB5 P5.4/KB4 CC4 P5.3/KB3 P5.2/KB2 CCLK P5.1/KB1 P5.0/KB0 PSEN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P3.7/RD/LED3 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 XTAL1 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 XTAL2 CVCC LI CVSS VCC ALE 48 47 46 45 44 43 42 P3.1/TxD P1.6/SS P2.7/A15 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 P4.1/MOSI P3.4/T0/LED1 P4.2/SCK P4.3/LED4 P3.6/WR/LED2 P4.4/LED5 RST P4.5/LED6
P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 41 40 39 38 37 36 35 34 33
P2.0/A8 P2.1/A9
AVCC PLLF
VQFP64
6
AT8xC5122/23
4202D-SCR-06/05
AVSS
CIO EA
D+ D-
AT8xC5122/23
Figure 2. PLCC68 Package Pinout (for engineering purpose only)
EA P1.7/CCLK1 VREF
P2.2/A10 AVCC
P2.3/A11 P2.4/A12
CIO
9876 DVCC P1.2/CPRES CC8 P5.7/KB7 P5.6/KB6 CRST P5.5/KB5 P5.4/KB4 CC4 P5.3/KB3 P5.2/KB2 CCLK P5.1/KB1 P5.0/KB0 PSEN VSS NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 N/A P3.1/TxD P1.6/SS P2.7/A15 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 P4.1/MOSI P3.4/T0/LED1 P4.2/SCK P4.3/LED4 P3.6/WR/LED2 P4.4/LED5 RST P4.5/LED6
PLCC68
P2.5/A13 P2.6/A14 N/A 52 51 50 49 48 47 46 45 44 XTAT1 XTAL2
P2.0/A8 P2.1/A9
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC CVCC LI CVSS VCC P0.4/AD4 P3.7/RD/LED3 P0.3/AD3 P0.2/AD2 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.1/AD1 P0.0/AD0 ALE NC : not connected N/A : not available
PLLF
D+ D-
AVSS
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4202D-SCR-06/05
Figure 3. QFN64 Package Pinout
P1.7/CCLK1 VREF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES CC8 P5.7/KB7 P5.6/KB6 CRST P5.5/KB5 P5.4/KB4 CC4 P5.3/KB3 P5.2/KB2 CCLK P5.1/KB1 P5.0/KB0 PSEN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P3.7/RD/LED3 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 XTAL1 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 XTAL2 CVCC LI CVSS VCC ALE 48 47 46 45 44 43 42 P3.1/TxD P1.6/SS P2.7/A15 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 P4.1/MOSI P3.4/T0/LED1 P4.2/SCK P4.3/LED4 P3.6/WR/LED2 P4.4/LED5 RST P4.5/LED6
P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 41 40 39 38 37 36 35 34 33
P2.2/A10
P2.0/A8 P2.1/A9
AVCC PLLF
D+ D-
QFN64
8
AT8xC5122/23
4202D-SCR-06/05
AVSS
CIO EA
AT8xC5122/23
AT89C5122DS version Figure 4. VQFP64 Package Pinout
P1.7/CCLK1 VREF
CIO VCC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES CC8 P5.7/KB7 P5.6/KB6 CRST P5.5/KB5 P5.4/KB4 CC4 P5.3/KB3 P5.2/KB2 CCLK P5.1/KB1 P5.0/KB0 PSEN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P3.7/RD/LED3 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 XTAL1 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 XTAL2 CVCC LI CVSS VCC ALE 48 47 46 45 44 43 42 P3.1/TxD P1.6/SS P2.7/A15 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 P4.1/MOSI P3.4/T0/LED1 P4.2/SCK P4.3/LED4 P3.6/WR/LED2 P4.4/LED5 RST P4.5/LED6
P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 41 40 39 38 37 36 35 34 33
P2.2/A10
P2.0/A8 P2.1/A9
AVCC PLLF
D+ D-
VQFP64
AVSS
9
4202D-SCR-06/05
Figure 5. QFN64 Package Pinout
P1.7/CCLK1 VREF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES CC8 P5.7/KB7 P5.6/KB6 CRST P5.5/KB5 P5.4/KB4 CC4 P5.3/KB3 P5.2/KB2 CCLK P5.1/KB1 P5.0/KB0 PSEN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P3.7/RD/LED3 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 XTAL1 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 XTAL2 CVCC LI CVSS VCC ALE 48 47 46 45 44 43 42 P3.1/TxD P1.6/SS P2.7/A15 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 P4.1/MOSI P3.4/T0/LED1 P4.2/SCK P4.3/LED4 P3.6/WR/LED2 P4.4/LED5 RST P4.5/LED6
P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 41 40 39 38 37 36 35 34 33
P2.2/A10
P2.0/A8 P2.1/A9
AVCC PLLF
D+ D-
QFN64
10
AT8xC5122/23
4202D-SCR-06/05
AVSS
CIO VCC
AT8xC5122/23
Low Pin Count Package Description
AT8xC5122 and AT83C5123 versions Figure 6. PLCC28 Package Pinout
AVCC PLLF CIO VREF AVSS
4 3 2 1 28 27 26
DVCC P1.2/CPRES CC8 CRST CC4 CCLK VSS
D+ D-
5 6 7 8 9 10 11
PLCC28
25 24 23 22 21 20 19
P3.1/TxD P3.0/RxD P3.2/INT0/LED0 P3.3/INT1 P3.4/T0/LED1 P3.6/LED2 RST
12 13 14 15 16 17 18
VCC P3.7/LED3 XTAL1 XTAL2 AVSS CVCC LI CVSS D+
AT83C5123 version
Figure 7. VQFP32 Package Pinout
CIO P1.7/CCLK1
32 31 30 29 28 27 26 25
DVCC P1.2/CPRES CC8 CRST CC4 CCLK P5.0 VSS
DAVCC PLLF
VREF
1 2 3 4 5 6 7 8
CVCC
VQFP32
24 23 22 21 20 19 18 17
P3.1/TxD P1.6 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P3.3/INT1 P3.4/T0/LED1 P3.6/LED2
9 10 11 12 13 14 15 16
LI CVSS P3.7/LED3 XTAL1 XTAL2 RST VCC
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4202D-SCR-06/05
Figure 8. QFN32 Package Pinout
CIO P1.7/CCLK1
DAVCC PLLF
VREF
32 31 30 29 28 27 26 25
DVCC P1.2/CPRES CC8 CRST CC4 CCLK P5.0 VSS
AVSS
D+
1 2 3 4 5 6 7 8
CVCC
QFN32
24 23 22 21 20 19 18 17
P3.1/TxD P1.6 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P3.3/INT1 P3.4/T0/LED1 P3.6/LED2
9 10 11 12 13 14 15 16
LI CVSS P3.7/LED3 XTAL1 XTAL2 RST VCC
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AT8xC5122/23
Pin Description
Table 2. Pin Description
PLCC68 PLCC28 VQFP64 VQFP32 QFN64 QFN32 Internal Power Supply VCC VCC VCC VCC VCC VCC VCC VCC ESD 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV I/O I/O I/O I/O I/O I/O I/O I/O I/O Reset Level Float Float Float Float Float Float Float Float Alt AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Reset Config P0 P0 P0 P0 P0 P0 P0 P0 Conf 1 Conf 2 KB_OUT KB_OUT KB_OUT KB_OUT KB_OUT KB_OUT KB_OUT KB_OUT Conf 3 Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Led
Port P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
30 29 28 27 25 24 23 22
-
41 40 39 38 36 35 34 33
-
30 29 28 27 25 24 23 22
-
CVCC inactive at reset. ESD tested with a 10F on CVCC CIO 64 32 9 4 64 32 CVCC 6KV I/O 0 Port51 An external pull-up of 10K is recommended to support ICC's with too high internal pull-ups. CVCC inactive at reset ESD tested with a 10F on CVCC Weak & medium pull-up can be disconnected CVCC inactive at reset ESD tested with a 10F on CVCC CVCC inactive at reset ESD tested with a 10F on CVCC CVCC inactive at reset ESD tested with a 10F on CVCC
CC4
3
3
12
7
3
3
CVCC
6KV
I/O
0
Port51
P1.2
2
2
11
6
2
2
VCC
2KV
I/O
1
CPRES
Port51
CC4
9
5
18
9
9
5
CVCC
6KV
I/O
0
Port51
CCLK
12
6
21
10
12
6
CVCC
6KV
O
0
Push-pull
CRST
6
4
15
8
6
4
CVCC
6KV
O
0
Push-pull
P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
47 62 58 57 56 52 51 50
23 31 -
58 7 3 2 1 65 64 63
-
47 62 58 57 56 52 51 50
23 31 -
VCC VCC VCC VCC VCC VCC VCC VCC
2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV
I/O I/O I/O I/O I/O I/O I/O I/O
1 1 1 1 1 1 1 1
SS CCLK1 A8 A9 A10 A11 A12 A13
Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull KB_OUT KB_OUT KB_OUT KB_OUT KB_OUT KB_OUT Input WPU Input WPU Input WPU Input WPU Input WPU Input WPU
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Table 2. Pin Description (Continued)
VQFP64 VQFP32 PLCC68 PLCC28 QFN64 QFN32 Internal Power Supply VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ESD 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV 2KV I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Reset Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 KB0 KB1 KB2 KB3 KB4 Alt A14 A15 RxD TxD INT0 INT1 T0 T1 WR RD MISO MOSI SCK Reset Config Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Port51 Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull KB_OUT KB_OUT KB_OUT Input MPU Input MPU Input MPU Input WPD Input WPD Input MPU Input MPU Input MPU Input WPU Input WPU Input WPU Input WPU Input WPU LED4 LED5 LED6 LED2 LED3 Push-pull Push-pull KB_OUT KB_OUT Input WPU Input WPU LED1 Conf 1 Push-pull Push-pull Push-pull Push-pull Conf 2 KB_OUT KB_OUT KB_OUT KB_OUT Conf 3 Input WPU Input WPU Input WPU Input WPU LED0 Led
Port P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P5.0 P5.1 P5.2 P5.3 P5.4
49 46 45 48 43 41 39 44 36 26 42 40 38 37 35 33 14 13 11 10 8
22 24 20 19 18 21 17 13 7 -
62 57 56 59 54 52 50 55 47 37 53 51 49 48 46 44 23 22 20 19 17
24 25 23 22 21 20 16 -
49 46 45 48 43 41 39 44 36 26 42 40 38 37 35 33 14 13 11 10 8
22 24 20 19 18 21 17 13 7 -
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AT8xC5122/23
Table 2. Pin Description (Continued)
VQFP64 VQFP32 PLCC68 PLCC28 QFN64 QFN32 Internal Power Supply VCC VCC VCC ESD 2KV 2KV 2KV I/O I/O I/O I/O Reset Level 1 1 1 Alt KB5 KB6 KB7 Reset Input The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. RST 34 16 45 19 34 16 VCC I/0 This pin has an internal 10K pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. The output is active for at least 12 oscillator periods when an internal reset occurs. USB Positive Data Upstream Port D+ 60 29 5 2 60 29 DVCC I/O This pin requires an external serial resistor of 27 (AT8xC122) or 33 (AT83C5123) and a 1.5 K pull-up to VREF for full speed configuration. USB Negative Data Upstream Port D59 28 4 1 59 28 DVCC I/O This pin requires an external serial resistor of 27 (AT8xC122) or 33 (AT83C5123) USB Voltage Reference: 3.0 < VREF < 3.6 V VREF can be connected to D+ through a 1.5 K resistor. The VREF voltage is controlled by software. Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal or an external oscillator must be connected to this pin. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal circuit must be connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. External Access Enable (Only AT8xC5122) EA must be strapped to ground in order to enable the device to fetch code from external memory locations 0000h to FFFFh. EA/ VCC 63 8 63 VCC I If security level 1 is programmed, EA will be latched on reset. Warning : EA pin cannot be left floating. If the External Access Enable mode is not used, EA pin must be strapped to VCC. If this last condition is not met,the MCU may have an unpredictable behaviour. VCC (Only AT89C5122DS) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR's AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches Reset Config Port51 Port51 Port51 Conf 1 Push-pull Push-pull Push-pull Conf 2 Input WPD Input WPD Input WPD Conf 3 Input WPU Input WPU Input WPU Led
Port P5.5 P5.6 P5.7
7 5 4
-
16 14 13
-
7 5 4
-
VREF
XTAL 1 XTAL 2
61
30
6
3
61
30
AVCC
O
31
14
42
17
31
14
VCC
I
32
15
43
18
32
15
VCC
O
ALE
21
-
32
-
21
-
VCC
O
15
4202D-SCR-06/05
Table 2. Pin Description (Continued)
VQFP64 VQFP32 PLCC68 PLCC28 QFN64 QFN32 Internal Power Supply ESD I/O Reset Level Alt Reset Config Conf 1 Conf 2 Conf 3 Led
Port
PSEN
15
-
24
-
15
-
VCC
O
Program Strobe Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. PLL Low Pass Filter input Receives the RC network of the PLL low pass filter. Analog Supply Voltage
PLLF
54
26
67
27
54
26
AVCC
O
AVCC
55
27
68
28
55
27
PWR
AVCC is used to supply the internal 3.3V analog regulator which supplies the internal USB driver Supply Voltage
VCC
20
12
31
15
20
12
PWR
VCC is used to supply the internal 3.3V digital regulator which supplies the PLL, CPU core and internal I/O's DC/DC Input LI supplies the current for the charge pump of the DC/DC converter.
LI
18
10
29
13
18
10
PWR
- LI tied directly to VCC : the DC/DC converter must be configured in regulator mode. - LI tied to VCC through an external 10H coil : the DC/DC converter can be configured either in regulator or in pump mode. Card Supply Voltage
CVCC
17
9
28
12
17
9
PWR
CVCC is the ouput of internal DC/DC converter which supplies the Smart Card Interface. It must be connected to an external decoupling capacitor of 10 F with the lowest ESR as this parameter influences on the CVCC noise Digital Supply Voltage
DVCC
1
1
10
5
1
1
PWR
DVCC is the output of the internal analog 3.3V regulator which supplies the USB driver. This pin must be connected to an external 680nF decoupling capacitor if the USB interface is used. This output can be used by the application with a maximum of 10 mA.
CVSS
19
11
30
14
19
11
GND
DC/DC Ground CVSS is used to sink high shunt currents from the external coil Digital Ground VSS is used to supply the PLL, buffer ring and the digital core Analog Ground AVSS is used to supply the USB driver.
VSS AVSS
16 53
8 25
25 66
11 26
16 53
8 25
GND GND
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Typical Applications
Recommended External components
All the external components described in the figure and table below must be implemented as close as possible from the microcontroller package. Table 3. External Components Bill Of Materials
Reference Description R1 R2 USB Full Speed Pull-up USB pad serial resistor Value 1.5 K +/-10% 27 +/-10% 33 +/-10% 27 +/-10% R3 R4 R5 C1 C2 C3 C4 C5 C6 C7 USB pad serial resistor PLL filter resistor CIO Pull-up resistor Power Supply filter capacitor PLL filter capacitor PLL filter capacitor USB pad decoupling capacitor Smart Card clock filter capacitor DC/DC Converter decoupling capacitor DC/DC Converter filter capacitor 33 +/-10% 1.8 K +/-10% 10 K +/10% 100 nF +80/-20% 33 pF +/-10% 150 pF +/-10% 680 nF +/-30% 27 pF +/-10% 10 F +/-10% Low ESR 100 nF +80/-20% Comments All product versions For AT8xC5122 versions For AT83C5123 versions For AT8xC5122 versions For AT83C5123 versions All product versions All product versions All product versions All product versions All product versions All product versions. If USB interface is not used, this capacitor is optional All product versions. All product versions. This capacitor does not impact the USB Inrush Current All product versions All products versions C8 Power Supply decoupling capacitor 4.7 F +/-10% This capacitor impacts the USB Inrush Current. Maximum application capacitance allowed by the USB standard is 10 F. All product versions Optional capacitor for all product versions All product versions. Qualified component : Murata LQH32CN100K21L If DC/DC converter is not used at 5V, this inductance is optional.
C9 C10
Power Supply filter capacitor Reset capacitor
100 nF +80/-20C 10 F +/-10% 10 H +/- 10%
L1
DC/DC converter input inductance
Min rated current : 200 mA Min rated freq. : 4 MHz 8.0000 Mhz +/- 2500 ppm max ESR max : 100
Q1
Crystal
All product versions
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USB Keyboard with Smart Card Reader Using the AT8xC5122 and AT89C5122DS Versions
VCC VCC
C9 GND VCC GND VCC EA/VCC (1) 10mA Max C4 GND DVCC
C8 GND AVCC LEDx
C1 VCC
VCC L1 LI C6 C7 C1 VCC
USB
VBUS D+ DGND
VCC
R1 R2 R3
Smart Card
VREF D+ D-
CVCC CVSS CRST CCLK CC4 CIO CC8 CPRES
C5 GND GND C2 C3 C4 C7 C8 S1 R5 RST CLK C4 I/O C8 S1 S2 GND VCC
GND C0 C1 C2 C3 C4 C5 C6 C7 R00 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
KB0 KB1 KB2 KB3 KB4 KB5 KB6 KB7 P3[0-1,3-4] P2[0-7] P0[0-7]
Alternate Card
C1 C2 C3 C7 C5 VCC RST CLK I/O GND
CRST1 CCLK1 CIO1 GND RST Optional Capacitor
Keyboard Matrix
PLLF R4 C2 C3 GND GND AVSS VSS
C10 XTAL1 XTAL2 GND
Q1
Notes : 1 - Pin configuration depends on product versions
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USB Smart Card Reader Using the AT83C5123 Version
VCC VCC
C9 GND VCC EA 10mA Max C4 GND DVCC GND VCC
C8 GND AVCC LEDx
C1 VCC
VCC L1 LI C6 C7
Smart Card
C1 VCC C5 GND
USB
VBUS D+ DGND
VCC
R1 R2 R3
VREF D+ D-
CVCC CVSS CRST CCLK CC4 CIO CC8 CPRES
GND
GND
C2 C3 C4 C7 C8 S1 R5
RST CLK C4 I/O C8 S1 S2 GND
VCC
Alternate Card
C1 C2 C3 C7 C5 VCC RST CLK I/O GND
CRST1 CCLK1 CIO1 GND PLLF R4 C2 C3 GND GND Q1 AVSS VSS RST XTAL1 XTAL2 C10 GND
Optional Capacitor
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Memory Organization
The AT8xC5122/23 devices have separated address spaces for Program and Data Memory, as shown in Figure 13 on page 29, Figure 14 on page 31 and Figure 15 on page 32. The logical separation of Program and Data memory allows the Data Memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an-bit CPU. Nevertheless, 16-bit Data Memory addresses can also be generated through the DPTR register. Depending on the state of EA pin, the MCU fetches the code from internal or external program memory (ROMless mode) Warning : the EA pin can not be left floating, otherwise MCU may have an unpredictable behaviour. If EA is strapped to VCC, the MCU fetches the code from the internal program memory. The way the MCU works in this mode depends on the device version. See next paragraphs for further details. If the EA is strapped to GND, the MCU fetches the code from external program memory. This mode is common for all device versions wich supports it. After reset, the CPU begins the execution from location 0000h. There can be up to 64 KBytes of program memory. In this mode, the internal program memories are disabled. The hardware configuration for external program execution is shown in Figure 9. Figure 9. Executing from External Program Memory
AT8xC5122 A15:8 EXTERNAL PROGRAM MEMORY
Program Memory Managament
P2 ALE P0 AD7:0
A15:8 A7:0
Latch
A7:0 D7:0
PSEN#
OE
Note that the 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external Program Memory fetches. Port 0 serves as a multiplexed address/dat bus. It emits the low byte of the Program Counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the Program Memory. During the time that the low byte of the Program Counter is valid on P0, the signal ALE (Address Latch Enable) clocks the byte into an address latch. Meanwhile, Port 2 emits the high byte of the Program Counter (PCH). Then PSEN strobes the External Program Memory and the code byte is read into the MCU. PSEN is not activated and Ports P0 and P2 are not affected during internal program fetches.
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Data Memory Managament
All device versions implements : - 256 Bytes of RAM to increase data parameter handling and high level language usage - 512 bytes of XRAM (Extended RAM) to store program data. RAM Achitecture The internal RAM is mapped into three separate segments : * * * The Lower 128 bytes (addresses 00h to 7Fh) are directly and indirectly addressable. The Upper 128 bytes (addresses 80h to FFh) are indirectly addressable only. The Special Function Registers (SFRs) (addresses 80h to FFh) are directly addressable only.
The Upper 128 bytes and SFR's have the same address space but are physically separated. When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is in the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. * * Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings. If M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals. XRAM Achitecture Depending on the state of EXTRAM bit in AUXR register (See Table 5 on page 24), the MCU fetches data from internal or external XRAM. If EXTRAM=0 (reset condition), the MCU fetches the data from internal XRAM. The size of internal XRAM is configured by the bit XRS0 in AUXR register (See Table 5 on page 24). Table 4. XRAM Size Configuration
Address XRS0 0 1 XRAM size 256 Bytes (Reset condition) 512 bytes Start 000h 000h End 0FFh 1FFh
The XRAM logically occupies the first bytes of external data memory. The bit XRS0 can be used to hide a part of the available XRAM . This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. The XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. For example, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. 21
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An access to external XRAM memory locations higher than the accessible size of the memory (roll-over feature) will be performed with the MOVX DPTR instructions, with P0 and P2 as data/address busses, WR and RD as respectively write and read signals. Accesses above XRAM size can only be done by the use of DPTR. If EXTRAM=1 the MCU fetches the data from external XRAM Memory. There can be up to 64 KBytes of external XRAM Memory. The hardware configuration for external Data Memory Access is shown in Figure 10 Figure 10. Accessing to External XRAM Memory
AT8xC5122/23 P2 ALE P0 AD7:0 A15:8 EXTERNAL XRAM MEMORY A15:8 A7:0
Latch
A7:0 D7:0
RD# WR#
OE WR
MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port 2 outputs the highorder eight address bits (DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on WR and RD. Ports P0, P2 are not affected and RD, WR signals are not activated during access to internal XRAM. Note that external XRAM Memory access is only available on High Pin Count Packages. External Program Memory and external XRAM Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the ouput of the gate as the read strobe to the external program/data memory. RD PSEN
STROBE
Dual Data Pointer Register (DDPTR)
The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 7) that allow the program code to switch between them (Figure 11).
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Figure 11. Use of Dual Pointer
External Data Memory
7
0 DPS
DPTR1 DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
Assembly Language
; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 QU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ;increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. For example, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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Registers
Table 5. Auxiliary Register - AUXR (8Eh)
7 DPU Bit Number Bit Mnemonic Description Disable weak Pull-up 7 DPU 0 1 6-3 weak pull-up is enabled weak pull-up is disabled 6 5 4 3 2 XRS0 1 EXTRAM 0 AO
Reserved The value read from this bit is indeterminate. Do not change these bits. XRAM Size
2
XRS0
0 1
256 bytes (default) 512 bytes
EXTRAM bit Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting , XRAM selected. ALE Output bit 0 AO Cleared , ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used)(default). Set , ALE is active only when a MOVX or MOVC instruction is used.
Reset Value = 0XXX X000b
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Table 6. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5122
7 Bit Number 7-6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. Enable Boot ROM (CRAM / E2PROM version only) 5 ENBOOT Set this bit to map the Boot ROM from 8000h to FFFFh. If the PC increments beyond 7FFFh address, the code is fetch from internal ROM Clear this bit to disable Boot ROM. If the PC increments beyond 7FFFh address, the code is fetch from external code memory (C51 standard roll over function) This bit is forced to 1 at reset 4 3 2 1 0 GF3 0 DPS Reserved The value read from this bit is indeterminate. Do not change this bit. This bit is a general-purpose user flag. Always cleared. Reserved The value read from this bit is indeterminate. Do not change this bit. Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. 6 5 ENBOOT 4 3 GF3 2 0 1 0 DPS
Reset Value = XX1X XX0X0b (Not bit addressable) Table 7. Auxiliary Register 1 AUXR1- (0A2h) for AT83C5123
7 Bit Number 7-6 5 4 3 2 1 GF3 0 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. Reserved The value read from this bit is indeterminate. Do not change these bits. Reserved The value read from this bit is indeterminate. Do not change this bit. This bit is a general-purpose user flag. Always cleared. Reserved The value read from this bit is indeterminate. Do not change this bit. Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. 6 5 4 3 GF3 2 0 1 0 DPS
0
DPS
Reset Value = XXXX XX0X0b (Not bit addressable)
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Table 8. CRAM Configuration Register - RCON (D1h)
7 Bit Number 7-4 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. CRAM Memory Mapping Bit 3 RPS Set to map the CRAM memory during MOVX instructions Clear to map the XRAM memory during MOVX. This bit has priority over the EXTRAM bit. 2-0 Reserved The value read from this bit is indeterminate. Do not change these bits. 5 4 3 RPS 2 1 0 -
Reset Value = XXXX 0XXXb
AT8xC5122's CRAM and E2PROM Versions
The AT8xC5122's CRAM and E2PROM versions implements : - 32 KB of ROM mapped from 8000 to FFFF in which is embedded a bootloader for InSystem Programming feature - 32 KB of CRAM (Code RAM) , a volatile program memory mapped from 0000 to 7FFF In CRAM versions only : - 512 bytes of E2PROM can be optionally implemented to store permanent data In E2PROM version : - 32KB of E2PROM are implemented to store permanent code Warnings : - some bytes of user program memory space are reserved for bootloader configuration. Depending on the configuration, up to 256 bytes of code may be not available for the user code from 7F00h location. Refer to bootloader datasheet for further details. Port P3.7 may be used by the bootloader as a hardware condition at reset to select the In-System Programming mode. Once the bootloader has started, the P3.7 Port is no more used.
-
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AT8xC5122 Microcontroller FFFFh Bootloader P3.7
7FFFh 7F00h 7EFFh
Reserved
User code 0000h
When pin EA =1 and after the reset, the MCU begins the execution of the embedded bootloader from location F800h of the ROM. The bootloader implements an In-System Programming (ISP) mode which manages the transfer of the code in the volatile Program Memory (CRAM). For CRAM version, the code is supplied by the ATMEL's FLexible In-system Programming software (FLIP) through USB or UART interface For E2PROM version, the code is supplied from the internal code E2PROM or by FLIP. The state of pin P3.7 at reset determines the code source. If P3.7=1 (reset condition) the source is the internal E2PROM and the transfer takes about 1.5 seconds. If P3.7=0 the source is FLIP and the transfer time depends mainly on external conditions not related to bootloader. Once the code is running in CRAM, the roll-over condition (code fetched beyond address 7FFFh) depends on the state of ENBOOT bit of AUXR1 register (Table 6 on page 25). If ENBOOT=1 (reset condition) the MCU fetches the code from bootloader ROM. If ENBOOT=0, the MCU fetches the code from the external Program Memory. In this last case, PSEN is activated and Ports P0 and P2 are used to emit data and address signals. Warning : external Program Memory access is not allowed on Low Pin Count Packages.
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Using CRAM Memory
The CRAM is a read / write volatile memory that is mapped in the program memory space. Then when the power is switched off the code is lost and needs to be reload at each power up. In return, the CRAM enables a lot of flexibility in the code development as it can be programmed indefinitely. The user code running in the CRAM can perform read operations in CRAM itself by means of MOVC instructions like any C51 microcontroller does. Although the writing operations in CRAM are usually handled by the bootloader, it is possible for the user code to handle its own writing operations in CRAM as well. The user code must call API functions provided by the bootloader in the ROM memory. Refer to bootloader datasheet for further details about the use of these API functions. These API functions use a mechanism provided by the AT8xC5122 microcontroller. When the bit RPS is set in RCON register (Table 8 on page 26), the MOVX intructions are configured to write in CRAM instead of XRAM memory. However, due to C51 architecture, it is not possible for the user code to write directly in CRAM when it is itself running in CRAM. This is why the API functions must be called in order to have the code executing in ROM while the CRAM is written.
Figure 12. Read / Write Mechanisms in CRAM Memory
API functions BOOTLOADER RPS=1 MOVX CRAM
API Call
Writing operation
User code Read operation MOVC
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Figure 13. AT8xC5122's CRAM and E2PROM Versions (E2PROM version) FFFF 32K INTERNAL E2PROM (Read/Write) 8000 8000 Roll-Over PROGRAM MEMORY 7FFF FFFF Reset@ 32K INTERNAL ROM (Read Only) 8000 PSEN EA = 1 ENBOOT=1 FFFF 32K EXTERNAL PROGRAM MEMORY EXTERNAL PROGRAM MEMORY ENBOOT=0 EA = 0
32K
INTERNAL CRAM (Read/Write) 0000 Reset@ <0000> PSEN Optional (applicable only to CRAM version) 01FF 512 Bytes INTERNAL E2PROM 0000 On-Chip 256 bytes RAM Indirect Addressing FF EXTERNAL XRAM 0000 80 7F 00 RD WR Upper 128 Bytes RAM FF 80 Direct Addressing SFR Space
EXTRAM=0 FFFF
EXTRAM=1
EXTERNAL XRAM DATA MEMORY (Read / Write) 01FF On-chip 512 bytes XRAM 0000 0200 Roll-Over 01FF
Lower 128 Bytes RAM
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AT8xC5122's ROM Version
The AT8xC5122's ROM version implements : - 32 K of ROM mapped from 0000h to 7FFFh in which is embedded the user code. The ROM device is only factory programmable. - 512 bytes of E2PROM can be optionally implemented to store permanent data. With this option, the size of ROM is reduced to 30K. After the reset, the MCU begins the execution of the user code from location 0000h of the ROM. Access to external Program Memory is not allowed.
Security Level
There are two security levels (applicable to High Pin Count packages only) : Table 9. Security Levels Description
Security Level 1 Protection description No protection lock enabled MOVC instruction executed from external Program Memory is disabled when fetching code bytes from internal Program Memory EA is sampled and latched on reset. External code execution is enabled.
2
The security level 2 can be used to protect the user code from piracy. This option is configured at factory and must be requested by the customer at order time.
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Figure 14. AT8xC5122's ROM Version EA=1 FFFF EA=0
EXTERNAL
PROGRAM MEMORY (Read only)
8000 Roll-Over 7FFF INTERNAL 32K ROM 0000 RESET@ <0000> PSEN
EXTERNAL
EXTRAM=0 FFFF
EXTRAM=1
Optional 01FF
EXTERNAL XRAM 0200 Roll-Over 01FF On-chip 512 bytes XRAM 0000 0000 01FF EXTERNAL XRAM
512 Bytes INTERNAL E2PROM 0000 On-Chip 256 bytes RAM Indirect Addressing FF 80 7F 00 Upper 128 Bytes RAM FF 80 Direct Addressing SFR Space
DATA MEMORY (Read / Write)
Lower 128 Bytes RAM
RD
WR
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AT83C5123 Version
The AT83C5123 device is a low pin count version of the AT8xC5122. The ROM version implements : - 30 KB of ROM mapped from 0000 to 77FF in which is embedded the user code. The ROM device is only factory programmable. - 512 bytes of E2PROM can be optionally implemented to store permanent data
Figure 15. AT83C5123's Device
7FFF INTERNAL 30K ROM RESET@ <0000>
PROGRAM MEMORY (Read only)
OPTIONAL 01FF 512 Bytes INTERNAL E2PROM 0000
On-Chip 256 bytes RAM Indirect Addressing FF 80 Upper 128 Bytes RAM FF 80 Direct Addressing SFR Space
DATA MEMORY (Read / Write)
01FF On-chip 512 bytes XRAM 0000
7F 00
Lower 128 Bytes RAM
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Special Function Registers (SFR's)
Introduction
The Special Function Registers (SFRs) of the AT8xC5122/23 can be ranked into the following categories: * * * * * * * * * * * * * C51 Core Registers: ACC, B, DPH, DPL, PSW, SP System Configuration Registers: PCON, CKRL, CKCON0, CKCON1, CKSEL, PLLCON, PLLDIV, AUXR, AUXR1, RCON I/O Port Registers: P0, P1, P2, P3, P4, P5, PMOD1, PMOD2 Timer Registers: TCON, TH0, TH1, TMOD, TL0, TL1 Watchdog (WD) Registers: WDTRST, WDTPRG Serial I/O Port Registers: SADDR, SADEN, SBUF, SCON Baud Rate Generator (BRG) Registers: BRL, BDRCON System Interrupt Registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 Smart Card Interface (SCI) Registers: SCSR, SCCON/SCETU0, SCISR/SCETU1, SCIER/SCIIR, SCIBUF, SCGT0/SCWT0, SCGT1/SCWT1, SCICR/SCWT2, SCICLK DC/DC Converter Registers: DCCKPS Keyboard Interface Registers: KBE, KBF, KBLS Serial Port Interface (SPI) Registers: SPCON, SPSTA, SPDAT Universal Serial Bus (USB) Registers:USBCON, USBADDR, USBINT, USBIEN, UEPNUM, UEPCONX, UEPSTAX, UEPRST, UEPINT, UEPIEN, UEPDATX, UBYCTX, UFNUML, UFNUMH LED Controller Registers: LEDCON0, LEDCON1
*
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AT8xC5122 Version
Bit addressable 0/8 F8h UEPINT 0000 0000 B 0000 0000 P5 1111 1111 ACC 0000 0000 LEDCON1 XX00 0000 UBYCTX 0000 0000 LEDCON0 0000 0000 1/9 2/A 3/B Not bit addressable 4/C 5/D 6/E 7/F
F0h
E8h
E0h D8h D0h
PSW 0000 0000
RCON XXXX 0XXX
UEPCONX 1000 0000
UEPRST 0000 0000 UEPSTAX 0000 0000 UEPDATX 0000 0000
C8h SCICLK (1) C0h P4 1111 1111 0X10 1111 SCWT3
(1)
S1 C R S0
UEPIEN 0000 0000
SPCON 0001 0100
SPSTA 0000 0000
SPDAT 1111 1111
USBADDR 1000 0000
UEPNUM 0000 0000
0000 0000 IPL0 X000 000 SADEN 0000 0000 UFNUML 0000 0000 UFNUMH 0000 0000 USBCON 0000 0000 SCGT0 (1) 0000 1100 SCWT0
(1)
B8h
USBINT 0000 0000 SCGT1(1) XXXX XXX0 SCWT1
(1)
USBIEN 0000 0000 SCICR (1) 0000 0000 SCWT2
(1)
DCCKPS 0000 0000
S1 C R S0
B0h
P3 1111 1111
IEN1 XXXX X000
IPL1 00XX 00X0
IPH1 00XX 00X0
IPH0 X000 0000
1000 0000 SCETU0 (1) A8h IEN0 0000 0000 SADDR 0000 0000 SCIBUF XXXX XXXX SCSR X000 1000 0111 0100 SCCON
(1)
0010 0101 SCETU1 (1) XXXX X001 SCISR
(1)
0000 0000 SCIER
(1)
S1 C R S0
0X00 0000 SCIIR (1) 0X00 0000 WDTRST XXXX XXXX WDTPRG XXXX X000
0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 ISEL 0000 0100 SBUF XXXX XXXX PMOD0(2) 0000 0000 TMOD 0000 0000 SP 0000 0111 TL0 0000 0000 DPL 0000 0000 TL1 0000 0000 DPH 0000 0000 TH0 0000 0000 PMOD1 0000 0000 AUXR1 XX1X 0XX0 BRL 0000 0000 PLLCON XXXX X000 BDRCON XXX0 0000 PLLDIV 0000 0000 KBLS 0000 0000
10X0 0000
A0h
98h
KBE 0000 0000
KBF 0000 0000 CKRL XXXX 1111
90h
88h
TH1 0000 0000 CKSEL XXXX XXX0
AUXR 0XXX X000
CKCON0 X0X0 X000 PCON 00X1 0000
80h
Notes:
1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in.
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AT83C5123 Version
Bit addressable 0/8 F8h UEPINT 0000 0000 B 0000 0000 P5 XXXX XXX1 ACC 0000 0000 UBYCTX 0000 0000 LEDCON0 0000 0000 1/9 2/A 3/B Not bit addressable 4/C 5/D 6/E 7/F
F0h
E8h
E0h D8h D0h C8h
PSW 0000 0000
UEPCONX 1000 0000
UEPRST 0000 0000 UEPSTAX 0000 0000 UEPDATX 0000 0000
S1 C R S0
SCICLK (1) C0h P4 11XX XXXX 0X10 1111 SCWT3
(1)
UEPIEN 0000 0000
USBADDR 1000 0000
UEPNUM 0000 0000
0000 0000 IPL0 X000 000 SADEN 0000 0000 UFNUML 0000 0000 UFNUMH 0000 0000 USBCON 0000 0000 SCGT0 (1) 0000 1100 SCWT0
(1)
B8h
USBINT 0000 0000 SCGT1(1) XXXX XXX0 SCWT1
(1)
USBIEN 0000 0000 SCICR (1) 0000 0000 SCWT2
(1)
DCCKPS 0000 0000
S1 C R S0
B0h
P3 1111 1111
IEN1 X0XX 0XXX
IPL1 X0XX 0XXX
IPH1 X0XX 0XXX
IPH0 X000 0000
1000 0000 SCETU0 (1) A8h IEN0 0000 0000 SADDR 0000 0000 SCIBUF XXXX XXXX SCSR X000 1000 0111 0100 SCCON
(1)
0010 0101 SCETU1 (1) XXXX X001 SCISR
(1)
0000 0000 SCIER
(1)
S1 C R S0
0X00 0000 SCIIR
(1)
CKCON1 XXXX XXX0
0000 0000 ISEL 0000 0100 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 SBUF XXXX XXXX PMOD0 00XX 0XXX TMOD 0000 0000 SP 0000 0111 TL0 0000 0000 DPL 0000 0000 TL1 0000 0000 DPH 0000 0000 TH0 0000 0000 PMOD1 XXXX 00XX AUXR1 XXXX 0XX0 BRL 0000 0000 PLLCON XXXX X000 BDRCON XXX0 0000 PLLDIV 0000 0000
10X0 0000
0X00 0000 WDTRST XXXX XXXX WDTPRG XXXX X000
A0h
98h
90h
CKRL XXXX 1111 TH1 0000 0000 CKSEL XXXX XXX0 AUXR 0XXX X000 CKCON0 X0X0 X000 PCON 00X1 0000
88h
80h
Notes:
1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in.
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SFR's Description
Table 10. C51 Core SFRs
Mnemonic ACC B PSW SP DPL DPH Add Name E0h Accumulator F0h B Register D0h Program Status Word 81h Stack Pointer 82h 83h Data Pointer Low byte (LSB of DPTR) Data Pointer High byte (MSB of DPTR) CY AC F0 RS1 SP DPL DPH 7 6 5 4 ACC B RS0 OV F1 P 3 2 1 0
Table 11. Clock SFRs
Mnemonic PCON CKCON0 CKCON1 CKSEL CKRL PLLCON PLLDIV AUXR AUXR1 RCON (1) Add Name 87h Power Controller 8Fh Clock Controller 0 AFh Clock Controller 1 85h Clock Selection 97h Clock Reload Register A3h PLL Controller Register A4h PLL Divider register 8Eh Auxiliary Register 0 A2h Auxiliary Register 1 D1h CRAM memory Configuration DPU ENBOOT(1) GF3 RPS R3-0 XRS0 CKREL 3-0 EXT48 N3-0 EXTRAM A0 DPS PLLEN PLOCK 7 SMOD1 6 SMOD0 WDX2 5 4 POF SIX2 3 GF1 2 GF0 T1X2 1 PD T0X2 0 IDL X2 SPIX2 CKS
Note:
1. Only for AT8xC5122
Table 12. I/O Port SFRs
Mnemonic P0(1) P1 P2(1) P3 P4(1) P5 PMOD0 PMOD1 Add Name 80h Port 0 90h Port 1 A0h Port 2 B0h Port 3 C0h Port 4 E8h Port 5 91h Port Mode Register 0 84h Port Mode Register 1 P3C1 P5HC1(1) P3C0 P5HC0(1) P2C1(1) P5MC1(1) 7 6 5 4 P0 P1 P2 P3 P4 P5 (only P5.0 for AT8xC5122) P2C0(1) P5MC0(1) CPRESRES P5LC1 P5LC0 P0C1(1) P4C1(1) P0C0(1) P4C0(1) 3 2 1 0
Note:
1. Only for AT8xC5122
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Table 13. Timers SFRs
Mnemonic TH0 TL0 TH1 TL1 TCON TMOD Add Name 8Ch Timer/Counter 0 High byte 8Ah Timer/Counter 0 Low byte 8Dh Timer/Counter 1 High byte 8Bh Timer/Counter 1 Low byte 88h 89h Timer/Counter 0 and 1 control Timer/Counter 0 and 1 Modes TF1 GATE1 TR1 C/T1# TF0 M11 TR0 M01 7 6 5 4 TH0 TL0 TH1 TL1 IE1 GATE0 IT1 C/T0# IE0 M10 IT0 M00 3 2 1 0
Table 14. Watchdog SFRs
Mnemonic WDTRST WDTPRG Add Name A6h Watchdog Timer Reset A7h Watchdog Timer Program 7 6 5 4 WDTRST S2-0 3 2 1 0
Table 15. Serial I/O Ports SFRs
Mnemonic SCON SBUF SADEN SADDR Add Name 98h Serial Control 99h Serial Data Buffer B9h Slave Address Mask A9h Slave Address 7 FE/SM0 6 SM1 5 SM2 4 REN SBUF SADEN SADDR 3 TB8 2 RB8 1 TI 0 RI
Table 16. Baud Rate Generator SFRs
Mnemonic BRL BDRCON Add Name 9Ah Baud Rate Reload 9Bh Baud Rate Control BRR 7 6 5 4 BRL TBCK RBCK SPD M0SRC 3 2 1 0
Table 17. Interrupt SFRs
Mnemonic IEN0 IEN1 IPL0 Add Name A8h Interrupt Enable Control 0 B1h Interrupt Enable Control 1 B8h Interrupt Priority Control Low 0 7 EA EUSB PSL 6 5 4 ES 3 ET1 ESCI PT1L 2 EX1 ESPI
(1)
1 ET0
0 EX0 EKB(1)
PX1L
PT0L
PX0L
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Table 17. Interrupt SFRs
Mnemonic IPH0 IPL1 IPH1 ISEL Add Name B7h B2h B3h Interrupt Priority Control High 0 Interrupt Priority Control Low 1 Interrupt Priority Control High 1 CPLEV PUSBL PUSBH PRESIT RXIT 7 6 5 4 PSH 3 PT1H PSCIL PSCIH OELEV 2 PX1H PSPIL(1) PSPIH(1) OEEN PRESEN 1 PT0H 0 PX0H PKBL(1) PKBH(1) RXEN
A1h Interrupt Enable Register
Note:
1. Only for AT8xC5122
Table 18. SCIB SFRs
Mnemonic SCGT0 SCGT1 SCWT0 SCWT1 SCWT2 SCWT3 SCICR SCCON SCETU0 SCETU1 SCISR Add Name B4h B5h B4h B5h B6h C1h B6h ACh Smart Card Transmit Guard Time Register 0 Smart Card Transmit Guard Time Register 1 Smart Card Character/ Block Waiting Time Register 0 Smart Card Character/ Block Waiting Time Register 1 Smart Card Character/ Block Waiting Time Register 2 Smart Card Character/ Block Waiting Time Register 3 Smart Card Interface Control Register Smart Card Interface Contacts Register RESET CLK CARDDET VCARD1-0 CARDC8 CARDC4 WT7 - 0 WT15-8 WT23-16 WT31-24 UART CARDIO WTEN CREP CONV 7 6 5 4 GT7 - 0 GT8 3 2 1 0
CARDCLK CARDRST CARDVCC
ACh Smart Card ETU Register 0 ADh Smart Card ETU Register 1 ADh Smart Card UART Interface Status Register (Read only) COMP SCTBE CARDIN
ICARDOVF
ETU7 - 0 ETU10-8 VCARDOK SCWTO SCTC SCRC SCPE
SCIIR
Smart Card UART Interrupt AEh Identification Register (Read only) AEh ABh Smart Card UART Interrupt Enable Register Smart Card Selection Register
SCTBI
ICARDERR
VCARDERR
SCWTI
SCTI
SCRI
SCPI
SCIER SCSR
ESCTBI BGTEN
ICARDER
EVCARDER
ESCWTI
ESCTI
ESCRI SCCLK1
ESCPI SCRS
CREPSEL
ALTKPS1-0
SCIBUF
AAh Smart Card Buffer Register
Can store a new byte to be transmitted on the I/O pin when SCTBE is set. Bit ordering on the I/O pin depends on the convention Provides the byte received from the I/O pin when SCRI is set. Bit ordering on the I/O pin depends on the convention.
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Table 18. SCIB SFRs
Mnemonic SCICLK Add Name C1h Smart Card Frequency Prescaler Register 7 XTSCS(1) 6 5 4 3 2 SCICLK5-0 1 0
Note:
1. Only for AT8xC5122
Table 19. DC/DC SFRs
Mnemonic DCCKPS Add Name BFh DC/DC Converter Reload Register 7 MODE 6 OVFADJ 5 4 3 2 1 0
BOOST[1-0]
DCCKPS3-0
Table 20. Keyboard SFRs
Mnemonic KBF
(1)
Add Name 9Eh Keyboard Flag Register 9Dh 9Ch Keyboard Input Enable Register Keyboard Level Selector Register
7
6
5
4 KBE7 - 0 KBF7 - 0 KBLS7 - 0
3
2
1
0
KBE(1) KBLS(1)
Note:
1. Only for AT8xC5122
Table 21. SPI SFRs
Mnemonic SPCON(1) SPSTA(1) SPDAT(1) Add Name C3h Serial Peripheral Control C4h Serial Peripheral StatusControl 7 SPR2 SPIF 6 SPEN WCOL 5 SSDIS 4 MSTR MODF R7 - 0 3 CPOL 2 CPHA 1 SPR1 0 SPR0
C5h Serial Peripheral Data
Notes:
1. Only for AT8xC5122
Table 22. USB SFRs
Mnemonic USBCON USBADDR USBINT USBIEN UEPNUM UEPCONX UEPSTAX UEPRST UEPINT Add Name BCh USB Global Control C6h USB Address BDh USB Global Interrupt BEh USB Global Interrupt Enable 7 USBE FEN WUPCPU EORINT 6 SUSPCLK 5
SDRMWUP
4 DETACH
3 UPRSM UADD6-0 SOFINT ESOFINT
2 RMWUPE
1 CONFG
0 FADDEN
SPINT ESPINT EPNUM3-0
EWUPCPU EEORINT
C7h USB Endpoint Number D4h USB Endpoint X Control CEh USB Endpoint X Status D5h USB Endpoint Reset F8h USB Endpoint Interrupt EPEN DIR NAKIEN RXOUTB1 EP6RST EP6INT NAKOUT STALLRQ EP5RST EP5INT NAKIN TXRDY EP4RST EP4INT DTGL STL/CRC EP3RST EP3INT
EPDIR RXSETUP EP2RST EP2INT
EPTYPE1 RXOUTB0 EP1RST EP1INT
EPTYPE0 TXCMP EP0RST EP0INT
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Table 22. USB SFRs
Mnemonic UEPIEN UEPDATX UBYCTX UFNUML UFNUMH Add Name C2h USB Endpoint Interrupt Enable 7 6 EP6INTE 5 EP5INTE 4 EP4INTE 3 EP3INTE 2 EP2INTE 1 EP1INTE 0 EP0INTE
CFh USB Endpoint X Fifo Data E2h USB Byte Counter Low (EPX)
FDAT7 - 0 BYCT6-0 FNUM7 - 0 CRCOK CRCERR FNUM10-8
BAh USB Frame Number Low BBh USB Frame Number High
Table 23. LED SFRs
Mnemonic LEDCON0 LEDCON1(1) Add Name F1h LED Control 0 E1h LED Control 1 7 LED3 6 5 LED2 LED6 4 3 LED1 LED5 2 1 LED0 LED4 0
Note:
1. Only for AT8xC5122
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Clock Controller
The clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the CPU core and peripherals are generated by this controller. The on-chip oscillator is composed of a single-stage inverter and a parallel feedback resistor. The XTAL1 and XTAL2 pins are respectively the input and the output of the inverter, which can be configured with off-chip components as a Pierce oscillator (see Figure 16). The on-chip oscillator has been designed and optimized to work with an external 8 MHz crystal and very few load capacitance. Then external load capacitors are not needed given that : - - the internal capacitance of the microcontroller and the stray capacitance of circuit board are enough to ensure a stable oscillation a very high accuracy on the oscillation frequency is not needed
On-Chip Oscillator
The circuit works on its fundamental frequency at 8 MHz. Figure 16. Oscillator Schematic Microcontroller
To internal clock circuitry Feedback Resistor
XTAL1
8 MHz
XTAL2
C1 GND GND
C2
C1 and C2 represents the internal capacitance of the microcontroller and the stray capacitance of the circuit board. It is recommended to implement the crystal as close as possible from the microcontroller package. Quartz Specification The equivalent circuit of a crystal is represented on the figure below : L1 C1 R1
C0
The Equivalent Serial Resistance R1 must be lower than 100 Ohm.
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Phase Lock Loop (PLL)
PLL Description The AT8xC5122/23's PLL is used to generate internal high frequency clock synchronized with an external low-frequency. Figure 17 shows the internal structure of the PLL. The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the clock generation. When the PLL is locked, the bit PLOCK in PLLCON register is set. The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PLLF pin (see Figure 18). Value of the filter components are detailed in the Section "DC Characteristics". The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF produced by the charge pump. It generates a square wave signal: the PLL clock. The CK_PLL frequency is defined by the follwing formula: FCK_PLL = FCK_XTAL1 * (R+1) / (N+1) Figure 17. PLL Block Diagram and Symbol
PLLF Up PFLD Down PLOCK
PLLCON.0
PLLCON.1
PLLEN N Divider
CK_XTAL1
N3:0
CHP
VREF
VCO
CK_PLL
R divider R3:0
Figure 18. PLL Filter Value
PLLF 1,8 K 150 pF
VSS VSS
33 pF
PLL Programming
The PLL must be programmed to work at 96 MHz frequency by means of PLLCON and PLLDIV registers. As soon as the PLL is enabled, the firmware must wait for the lock bit status to ensure that the PLL is ready.
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Figure 19. PLL Programming Flow
PLL Programming
Configure Dividers N3:0= xxxxb R3:0= xxxxb
Enable PLL PLLEN= 1
PLL Locked? PLOCK= 1?
Clock Tree Architecture
The clock controller outputs several different clocks as shown in Figure 20: * * a clock for the CPU core a clock for the peripherals which is used to generate the timers, watchdog, SPI, UART, and ports sampling clocks. This divided clock will be used to generate the alternate card clock. a clock for the USB a clock for the SCIB controller a clock for the DC/DC converter
* * *
These clocks are enabled or not depending on the power reduction mode as detailed in Section "Power Management", page 180. These clocks are generated using four presacalers defined in the table below:
Prescaler PR1 PR2 PR3 PR4 Register CKRL SCICLK SCSR DCCKPS Reload Factor CKRL[0:3] SCICLK[0:5] ALTKPS[0:1] DCCKPS[3:0] Function CPU & Peripheral clocks Smart card Alternate card DC/DC
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Figure 20. Clock Tree Diagram
PR4
DCCKPS[3:0] CKCON0.X or CKCON1.0 CK_DCDC
DC/DC Converter
PeriphX2
1
CKCON0.0
X2
1 0
CK_PERIPH
Peripherals CK_T0 CK_T1 CK_SI CK_WD CK_SPI
1/2
0
CK_XTAL1 CK_PLL
PERIPH = T0, T1, SI, WD or SPI
0 1
PR1
CKRL[3:0]
0 1
CK_IDLE
CK_CPU
CPU IDL
PCON.0
CKS
CKSEL.0 CK_XTAL1
X2
CKCON0.0
XTAL1
PLL 96 MHz PLLEN
PLLCON.1
CK_PLL
PR3
SCSR[3:2] CK_IDLE
Alternate Card
XTAL2
CK_PLL CK_XTAL1
0 1
PR2
SCICLK[5:0]
<48 =48
CK_ISO
SCIB
PD
PCON.1
XTSCS
SCICLK.7
SCICLK[5:0]
EXT48
PLLCON.2
1/2
CK_XTAL1
CK_IDLE
0 1
CK_USB
USB
CPU and Peripheral Clocks
Two clocks sources are available for CPU and peripherals: - - on-chip oscillator a derivative of the PLL clock.
These clock sources are configured by the PR1 prescaler to generate the CPU core CK_CPU and the peripheral clocks: - - - - - - CK_IDLE for alternate card and peripherals registers access CK_T0 for Timer 0 CK_T1 for Timer 1 CK_SI for the UART CK_WD for the Watchdog Timer CK_SPI for SPI
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The CPU and peripherals clocks frequencies are defined in the table below.
CKS 0 0 1 1 X2 0 1 0 1 FCK_IDLE FCK_XTAL1/(2*(16-CKRL)) FCK_XTAL1 FCK_PLL/(2*(16-CKRL)) Not allowed
X1 and X2 Modes
Use of on-chip oscillator When the CPU and Peripherals clocks are fed by the on-chip oscillator, the CPU and Peripherals can be configured independently in X1 or X2 mode depending on the frequencies wanted by the user. There is however one exception : the periperals can be configured in X2 mode while the CPU remains in X1 mode. This exception is handled by the hardware and the user does not need to take care of. Table 1. X1 and X2 Mode Selection
CPU X1 mode X1 mode Peripherals X1 mode X2 mode Status Allowed (default configuration at reset) Not Allowed by the hardware Allowed X2 mode X1 mode Once the CPU is switched to X2 mode, the user is free to switch any of the peripherals to X1 mode Allowed X2 mode X2 mode Default configuration when CPU is switched to X2 mode FCK_IDLE = FCK_PERIPH FCK_IDLE = 2*FCK_PERIPH FCK_IDLE = FCK_PERIPH Frequenci
The X1 or X2 modes can be individually selected for the CPU and each peripheral by means of CKCON0 and CKCON1 registers. At reset, the CPU and Peripherals are set all by default to X1 mode. In this mode, changing any peripheral to X2 mode has no effect. When X2 bit is set in CKCON0 register, CPU and All peripherals are automatically switched to X2 mode. It is then possible for the user to individually switch any peripheral back to X1 mode. In X1 mode (X2 bit cleared in CKCON0 regsiter), the PR1 prescaler is active while it is bypassed in X2 mode (X2 bit set in CKCON0 register). The X1 mode is true only when the prescaler PR1 is set to 1/2 (default condition at reset).
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Figure 21. X1 mode
Crystal
8 MHz
PR1 prescaler
CPU frequency
4 MHz
1/2
Peripheral frequency
4 MHz
When the X1 mode is selected, the CPU and Peripherals work at 8Mhz / X1 Figure 22. X2 mode
Crystal
8 MHz
CPU frequency (X2 Mode)
8 MHz
Peripheral frequency (X2 mode)
8 MHz
Internal Prescaler 1/2
Peripheral frequency (X1 mode)
4 MHz
When the X2 mode is selected, the CPU works at 8 MHz / X2. The Peripherals can work at 8 MHz / X2 or 8 MHz / X1. When the PR1 prescaler is different from 1/2, the usual X1 mode can not be defined. In this case, it is necessary to define a X1 or X2 equivalent mode from equivalent clock circuits. Example : PR1=1/8, X2=0. In this configuration, the CPU works at 1 MHz. This frequency could also be obtained by an equivalent clock circuit where the on-chip oscillator would run at 2 MHz in X1 mode or at 1 MHz in X2 mode. So we can say that the CPU works at 2 MHz / X1 or 1MHz / X2. As the X2 bit is cleared in CKCON0 register, we have FCK_IDLE = FCK_PERIPH.
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Crystal
8 MHz
PR1 Prescaler 1/8
CPU frequency
1 MHz
PERIPH frequency
1 MHz
(Equivalent to)
External Clock
2 MHz
X1 mode selected
CPU frequency
1 MHz
1/2
PERIPH frequency
1 MHz
(Equivalent to)
External Clock
1 MHz
X2 mode selected
CPU frequency
1 MHz
PERIPH frequency
1 MHz
Use of PLL Clock
When the CPU clock is fed by the PLL, the X2 mode is forbidden. The bit X2 must always remain cleared in CKCON0 register. As the PR1 prescaler is always different from 1/2, the usual X1 mode can not be defined. So it is necessary to define an equivalent X1 or X2 mode from equivalent clock circuits, as in previous section. Example: PR1=1/4, PLL feeds the CPU. The CPU works in this case at 24 MHz. This frequency could also be obtained by an equivalent clock circuit where the on-chip oscillator would run at 48 MHz in X1 mode or at 24 Mhz in X2 mode. So we can say that in this configuration, the CPU works at 48 MHz / X1 or 24 MHz / X2 (See figures below). As the X2 bit is cleared in CKCON0 register, we have always FCK_IDLE = FCK_PERIPH.
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PLL
96 MHz
Prescaler 1/4
CPU frequency
24 MHz
PERIPH frequency
24 MHz
(Equivalent to)
External Clock
48 MHz
X1 mode selected
CPU frequency
24 MHz
1/2
PERIPH frequency
24 MHz
(Equivalent to)
External Clock
24 MHz
X2 mode selected
CPU frequency
24 MHz
PERIPH frequency
24 MHz
SCIB Clock
The Smart Card Interface Block (SCIB) uses two clocks : - - The first one, CK_IDLE, is the peripheral clock used for the interface with the microcontroller. The second one, CK_ISO, is independant from the CPU clock and is generated from the PLL or XTAL1 output. PR2, a 6-bit prescaler, will be used to generate: 12/9.6/8/6.85/6/5.33/4.8/4.36/ ..../1MHz frequencies. SCIB clock frequency must be lower than CPU clock frequency.
During SCIB Reset, the CK_ISO input must be in the range 1 - 5 MHz according to ISO 7816. The SCIB clocks frequency is defined in Figure 42 on page 74 and Table 42 on page 74. Two conditions must be met for a correct use of the SCIB: * * CK_CPU > 4/3 * CK_ISO and CK_CPU < 6 * CK_ISO.
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If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn't work. If the CK_CPU >= 6* CK_ISO, the programmer must take care in three cases: * * Read (or write) operation on a SCIB register followed immediatly with an other Read (or write) operation on the same register. Read (or write) operation on a SCIB register followed immediatly with an other Read (or write) operation on a linked register. The list of linked registers is in the table below.
Linked registers Write in SCICR and after read of SCETU0-1 Write in SCIBUF and after read of SCISR
*
Write operation on a register of the list below followed immediatly with a read operation on a SCIB register.
Wait after Write operation on this registers SCICR, SCIER, SCETU0-1,SCGT0-1, SCWT0-3,SCCON
To avoid any trouble, a delay must be added between the two accesses on the SCIB register. The SCIB must complete the first read (or write) operation before to receive the second. A solution is to add NOP (no operation) instructions. The number of NOP to add depends of the rate between CK_CPU and CK_ISO (see table below).
Min CLK_CPU CLK_CPU >= 6 * CLK_ISO CLK_CPU >= 12* CLK_ISO
Max CLK_CPU CLK_CPU <= 12 * CLK_ISO CLK_CPU <= 16 * CLK_ISO
Number of CPU cycles to add 6 ( example1 NOP) 12 ( example 2 NOP)
Alternate Card Clock
The alternate Card uses the peripheral clock divided by the PR3 prescaler. (1; 1/2; 1/4; 1/8 division ratio). See Section "Alternate Card", page 78 for the definition of the alternate clock. The DC/DC block needs a clock with a 50% duty cycle. The frequency must also be included in the range 3.68 MHz and 6 MHz. The PR4 prescaler is used to configure the DC/DC frequency.
DC/DC Converter Clock
XTAL1 (MHz) 8
DCCKPS3:0 value 0
Prescaler Factor 2
DC/DC converter CLK (MHz) 4
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USB Interface Clock
The USB Interface uses two clocks : - - The first one is the CPU clock used for the interface with the microcontroller, CK_IDLE. The second one is the CK_USB supplied from the PLL through a divider by 2.
Registers
Table 24. Clock Selection Register - CKSEL (S:85h)
7 6 5 4 3 2 1 0 CKS
Bit Number Bit Mnemonic Description 7:1 Reserved The value read from this bit is indeterminate. Do not set this bit. CPU Oscillator Select Bit 0 CKS Set this bit to connect CPU and Peripherals to PLL output. Clear this to to connect CPU and Peripherals to XTAL1 clock input.
Reset Value = XXXX XXX0b
Table 25. Clock Reload Register - CKRL (S:97h)
7 6 5 4 3 CKRL3 2 CKRL2 1 CKRL1 0 CKRL0
Bit Number Bit Mnemonic Description 7-4 Reserved The value read from this bit is indeterminate. Do not set this bit. Clock Reload register 3:0 CKRL3:0 Prescaler1 value Fck_cpu =[ 1 / 2*(16-CKRL)] * Fck_XTAL1
Reset Value = XXXX 1111b
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Table 26. Clock Configuration Register 0 - CKCON0 (S:8Fh)
7 6 WDX2 5 4 SIX2 3 2 T1X2 1 T0X2 0 X2
Bit Number Bit Mnemonic Description 7 Reserved The value read from this bit is indeterminate. Do not set this bit. Watchdog clock 6 WDX2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the PR1 prescaler. Set to select the PR1 output for this peripheral. 5 Reserved The value read from this bit is indeterminate. Do not set this bit. Enhanced UART clock (Mode 0 and 2) 4 SIX2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the PR1 prescaler. Set to select the PR1 output for this peripheral. 3 Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 1 clock 2 T1X2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the PR1 prescaler. Set to select the PR1 output for this peripheral. Timer 0 clock 1 T0X2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the PR1 prescaler. Set to select the PR1 output for this peripheral. System clock Control bit 0 X2 Cleared to select the PR1 output for CPU and all the peripherals . Set to bypass the PR1 prescaler and to enable the individual peripherals `X2' bits.
Reset Value = X0X0 X000b
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Table 27. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122
7 6 5 4 3 2 1 0 SPIX2
Bit Number Bit Mnemonic Description 7-4 3 Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI clock 0 SPIX2 This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Cleared to bypass the PR1 prescaler. Set to select the PR1 output for this peripheral.
Reset Value = XXXX XXX0b Table 28. PLL Control Register - PLLCON (S:A3h)
7 6 5 4 3 2 EXT48 1 PLLEN 0 PLOCK
Bit Number Bit Mnemonic Description 7-3 Reserved The value read from these bits is always 0. Do not set this bits. External 48 MHz Enable Bit 2 EXT48 Set this bit to select XTAL1 as USB clock. Clear this bit to select PLL as USB clock. SCIB clock is controlled by EXT48 bit and XTSCS bit. PLL Enable bit 1 PLLEN Set to enable the PLL. Clear to disable the PLL. PLL Lock Indicator 0 PLOCK Set by hardware when PLL is locked Clear by hardware when PLL is unlocked
Reset Value = 0000 0000b Table 29. PLL Divider Register - PLLDIV (S:A4h)
7 R3 6 R2 5 R1 4 R0 3 N3 2 N2 1 N1 0 N0
Bit Number Bit Mnemonic Description 7-4 3-0 R3:0 N3:0 PLL R Divider Bits PLL N Divider Bits
Reset Value = 0000 0000b
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I/O Port Definition
Ports vs Packages Table 30. I/O Number vs Packages
P0 VQFP64 QFN64 VQFP32 QFN32 PLCC28 8 P1 8 8 6 P2 8 P3 8 8 6 P4 6 P5 8 1 1 Total 46 17 13
Port 0
Port 0 has the following functions: - - Default function: Port 0 is an 8-bit I/O port. Alternate function: Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application, it uses strong internal pull-ups when emitting 1's and it can drive CMOS inputs without external pull-ups. Default configuration: open drain bi-directional I/O port. Port 0 pins that have 1's written to them float, and in this state they can be used as highimpedance inputs. Configuration 2: Low speed output, "KB_OUT" Configuration 3: Push-pull output
Port 0 has the following configurations: -
- -
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Port 1
Port 1 has the following functions: - - Default function : Only Port 1.2, P1.6 and P1.7 are standard I/O's; the other ports can be activated only with the SCIB function. Alternate function and configuration: see Table 31.
Table 31. Port 1 Description.
Alternate Function Port Signal Description Smart card interface function Card I/O Smart card interface function Card contact 8 Smart card interface function Card presence Smart card interface function Card contact 4 Smart card interface function Card clock Smart card interface function Card reset SS pin of the SPI function Configuration Mode Quasi-bidirectional port supplied by DC/DC converter Comments Low level at reset. Caution : if DPU bit is set in AUXR register, the weak-pull of the port is disabled Low level at reset Caution : if DPU bit is set in AUXR register, the weak-pull of the port is disabled
CIO
CC8
Quasi-bidirectional port supplied by DC/DC converter
P1.2
CPRES
Weak & medium pull-up's can be disconnected Quasi-bidirectional port supplied by VCC by CPRESRES bit in PMOD0 regsiter High Level at reset Quasi-bidirectional port supplied by DC/DC converter Push-Pull port supplied by DC/DC converter Push-Pull port supplied by DC/DC converter Quasi-bidirectional supplied by VCC Quasi-bidirectional supplied by VCC Alternate Card Clock function disabled Alternate Smart Card Clock enabled Quasi-bidirectional supplied by VCC Switched automatically to Push-pull (see Table 47 on page 82 ) Low level at reset Caution : if DPU bit is set in AUXR register, the weak-pull of the port is disabled Low level at reset
CC4
CCLK
CRST P1.6 SS
Low level at reset
P1.7
CCLK1
Alternate Card Clock output
Port 2
Port 2 has the following functions: - - Default function: Port 2 is an 8-bit I/O port. Alternate function 1: Port 2 is also the multiplexed high-order address during accesses to external Program and Data Memory. In this application, it uses strong internal pull-ups when emitting 1's and it can drive CMOS inputs without external pull-ups. Default configuration: Pseudo bi-directional "Port51" digital input/output with internal pull-ups. Configuration 1: Push-pull output Configuration 2: Low speed output, "KB_OUT Configuration 3: Input with weak pull-up, "WPU input"
Port 2 has the following configurations: - - - -
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Port 3 Port 3 has the following functions: - - - - Default function: Port 3 is an 8-bit I/O port. Alternate functions: see table below Default configuration: Pseudo bi-directional "Port51" digital input/output with internal pull-ups. Alternate configurations: See Table 32.
Port 3 has the following configurations:
Table 32. Port 3 Description
Alternate Functions Port P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 Signal RxD TxD INT0 INT1 T0 T1 WR Description Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface External interrupt 0 input/timer 0 gate control input External interrupt 1input/timer 1 gate control input Timer 0 counter input Timer 1 counter input External Data Memory write strobe; latches the data byte from port 0 into the external data memory External Data Memory read strobe; Enables the external data memory. Port 3 can drive CMOS inputs without external pull-ups LED2 Push-pull Push-pull KB_OUT KB_OUT Input WPU Input WPU LED1 Configurations Mode 1 Push-pull Push-pull Mode 2 KB_OUT KB_OUT Mode 3 Input WPU Input WPU LED0 Mode 4
P3.7
RD
LED3
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Port 4
Port 4 has the following functions: - - - - Default function: Port 4 is an 6-bit I/O port. Alternate functions: see table below Default configuration: Pseudo bi-directional "Port51" digital input/output with internal pull-ups. Alternate configurations: See Table 33.
Port 4 has the following configurations:
Table 33. Port 4 Description
Alternate Functions Port P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 Signal MISO MOSI SCK Description SPI Master In Slave Out I/O SPI Master Out Slave In I/O SPI clock Push-pull Push-pull Push-pull KB_OUT KB_OUT KB_OUT Input MPU Input MPU Input MPU Configurations Mode 1 Mode 2 Mode 3
Port 5
Port 5 has the following functions: - - - - Default function: Port 5 is an 8-bit I/O port. Alternate function 1: Port 5 is an 8-bit keyboard port KB0 to KB7. Default configuration: Pseudo bi-directional "Port51" digital input/output with internal pull-ups. Alternate configuration: see Table 34.
Port 5 has the following configurations:
Table 34. Port 5 Description
Configurations Port P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 Mode 1 Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Mode 2 Input MPU Input MPU Input MPU Input WPD Input WPD Input WPD Input WPD Input WPD Mode 3 Input WPU Input WPU Input WPU Input WPU Input WPU Input WPU Input WPU Input WPU Third cluster Second cluster First cluster Comments
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Port Configuration
Standard I/O P0 The P0 port is described in Figure 23. Figure 23. Standard Input/Output Port ADDR/DATA CONTROL Vcc
PMOS
1
NMOS
Pin
Port latch Data
0 MUX
Vss
Input Data
Quasi Bi-directional Port The default port output configuration for standard I/O ports is the quasi-bi-directional output that is common on the 80C51 and most of its derivatives. The "Port51" output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the port outputs a logic low state, it is driven strongly and is able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bi-directional output that serve different purposes. One of these pull-ups, called the weak pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up sources a very small current that will pull the pin high if it is left floating. The weak pull-up can be turned off by the DPU bit in AUXR register. A second pull-up, called the medium pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only the weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the medium pull-up and take the voltage on the port pin below its input threshold.
Note: for CIO, CC4, CC8 ports of SCIB interface , in input mode when the ICC (smart card) is driving the port pin :
- -
if 0 < Vin < CVCC/2 : weak pull-up is active (~100KOhm) if CVCC/2 < Vin < CVCC : weak (~100KOhm) and medium (~12KOhm) pullup's are active 57
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The "Port51" is described in Figure 24. Figure 24. Quasi Bi-directional Port
DPU (AUXR.7)
2 CPU CLOCK DELAY
vcc P Strong
vcc P Weak
vcc P Medium
Port Latch Data
N
Pin
Input Data
Vss
Push-pull Output Configuration
The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bi-directional output modes, but provides a continuous strong pullup when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. The Push-pull port configuration is shown in Figure 25. Figure 25. Push-pull Output
P
PMOS
Strong
Port latch Data
Pin N
NMOS
Input with Medium or Weak Pull-up Configuration
The input with pull-up (Input MPU and Input WPU) configuration is shown in Figure 26.
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Figure 26. Input with Pull-up
P
Stuck to 0 if Medium Stuck to 0 if Weak
P Weak
Medium
Input Data
Pin
Input with Weak Pull-down Configuration
The input with pull-down (input WPD) configuration is shown in Figure 27 Figure 27. Input with Pull-down
Input Data
N
1
Pin Weak
Low Speed Output Configuration
The low speed output with low speed tFALL and tRISE can drive keyboard. The current limitation of the LED2CTRL block requires a polarisation current of about 250 A. This block is automatically disabled in power-down mode. The low speed output configuration (KB_OUT) is shown in Figure 28. Figure 28. Low-speed Output
P Weak
PWEAKCTRL
Pin
Port latch Data PCON.1
NMOS
N N
LED2CTRL
LED Source Current
The LED configuration is shown in Figure 29.
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Figure 29. LED Source Current
Pin
NMOS
LEDx.0 Port Latch Data LEDx.1
LEDCTRL
N N
Notes:
1. When switching a low level, LEDCTRL device has a permanent current of about N mA/15 (N is 2, 4 or 8). 2. The port must be configured as standard C51 port by means of PMOD0 and PMOD1 registers and the level of current must be programmed by means of LEDCON0 and LEDCON1 registers before switching the led on.
Table 35. LED Source Current
LEDx.1 0 0 0 0 1 1 1 1 LEDx.0 0 0 1 1 0 0 1 1 Port Latch Data 0 1 0 1 0 1 0 1 NMOS 1 0 0 0 0 0 0 0 PIN 0 LED control disabled 1 0 LED mode 2 mA 1 0 LED mode 4 mA 1 0 LED mode 10 mA 1 Comments
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Registers
Table 36. Port Mode Register 0 - PMOD0 (91h) for AT8xC5122
7 P3C1 Bit Number 6 P3C0 5 P2C1 4 P2C0 3 CPRESRES 2 1 P0C1 0 P0C0
Bit Mnemonic Description Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only) 00 Quasi bi-directional
7-6
P3C1-P3C0
01 Push-pull 10 Output Low Speed 11 Input with weak pull-up Port 2 Configuration bits 00 Quasi bi-directional
5-4
P2C1-P2C0
01 Push-pull 10 Output Low Speed 11 Input with weak pull-down Card Presence Pull-up resistor
3
CPRESRES
Cleared to connect the internal 100K pull-up Set to disconnect the internal pull-up
2
-
Reserved The value read from this bit is indeterminate. Do not set this bit. Port 0 Configuration bits 00 C51 Standard P0
1-0
P0C1-P0C0
01 Reserved 10 Output Low Speed 11 Push-pull
Reset Value = 0000 0x00b Table 37. Port Mode Register 0 - PMOD0 (91h) for AT83C5123
7 P3C1 Bit Number 6 P3C0 5 4 3 CPRESRES 2 1 0 -
Bit Mnemonic Description Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only) 00 Quasi bi-directional
7-6
P3C1-P3C0
01 Push-pull 10 Output Low Speed 11 Input with weak pull-up
5-4
Reserved The value read from these bits are indeterminate. Do not set these bit. Card Presence Pull-up resistor
3
CPRESRES
Cleared to connect the internal 100K pull-up Set to disconnect the internal pull-up
2-0
-
Reserved The value read from these bits are indeterminate. Do not set these bit.
Reset Value = 00xx 0xxxb
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Table 38. Port Mode Register 1 - PMOD1 (84h) for AT8xC5122
7 P5HC1 Bit Number 6 P5HC0 5 P5MC1 4 P5MC0 3 P5LC1 2 P5LC0 1 P4C1 0 P4C0
Bit Mnemonic
Description Port 5 High Configuration bits (Applicable from P5.6 to P5.7 only) 00 Quasi bi-directional
7-6
P5HC1-P5HC0 01 Push-pull 10 Input with weak pull-down 11 Input with weak pull-up Port 5 Medium Configuration bits (Applicable from P5.3 to P5.5 only) 00 Quasi bi-directional
5-4
P5MC1-P5MC0 01 Push-pull 10 Input with weak pull-down 11 Input with weak pull-up Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only) 00 Quasi bi-directional
3-2
P5LC1-P5LC0 01 Push-pull 10 Input with medium pull-up 11 Input with weak pull-up Port 4 Configuration bits (Applicable from P4.3 to P4.5 only) 00 Quasi bi-directional
1-0
P4C1-P4C0
01 Push-pull 10 Output Low Speed 11 Input with medium pull-up
Reset Value = 0000 0000b Table 39. Port Mode Register 1 - PMOD1 (84h) for AT83C5123
7 Bit Number 7-4 6 Bit Mnemonic 5 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only) 00 Quasi bi-directional 3-2 P5LC1-P5LC0 01 Push-pull 10 Input with medium pull-up 11 Input with weak pull-up 1-0 Reserved The value read from this bit is indeterminate. Do not set this bit. 4 3 P5LC1 2 P5LC0 1 0 -
Reset Value = xxxx 00xxb
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Table 40. LED Port Control Register 0 - LEDCON0 (F1h)
7 LED3.1 6 LED3.0 5 LED2.1 4 LED2.0 3 LED1.1 2 LED1.0 1 LED0.1 0 LED0.0
Bit Number Bit Mnemonic Description Port LED3 Configuration bits 7-6 LED3 00 01 10 11 LED control disabled 2 mA current source when P3.7 is configured as Quasi-bi-directional mode 4 mA current source when P3.7 is configured as Quasi-bi-directional mode 10 mA current source when P3.7 is configured as Quasi-bidirect. mode
Port LED2 Configuration bits 5-4 LED2 00 01 10 11 LED control disabled 2 mA current source when P3.6 is configured as Quasi-bi-directional mode 4 mA current source when P3.6 is configured as Quasi-bi-directional mode 10 mA current source when P3.6 is configured as Quasi-bidirect. mode
Port LED1 Configuration bits 3-2 LED1 00 01 10 11 LED control disabled 2 mA current source when P3.4 is configured as Quasi-bi-directional mode 4 mA current source when P3.4 is configured as Quasi-bi-directional mode 10 mA current source when P3.4 is configured as Quasi-bidirect. mode
Port LED0 Configuration bits 1-0 LED0 00 01 10 11 LED control disabled 2 mA current source when P3.2 is configured as Quasi-bi-directional mode 4 mA current source when P3.2 is configured as Quasi-bi-directional mode 10 mA current source when P3.2 is configured as Quasi-bidirect. mode
Reset Value = 0000 0000b Table 41. LED Port Control Register 1- LEDCON1 (F1h) only for AT8xC5122
7 6 5 LED6.1 4 LED6.0 3 LED5.1 2 LED5.0 1 LED4.1 0 LED4.0
Bit Number Bit Mnemonic Description 7-6 Reserved The value read from this bit is indeterminate. Do not set this bit. Port LED6 Configuration bits 5-4 LED6 00 01 10 11 LED control disabled 2 mA current source when P4.5 is configured as Quasi-bi-directional mode 4 mA current source when P4.5 is configured as Quasi-bi-directional mode 10 mA current source when P4.5 is configured as Quasi-bidirect. mode
Port LED5 Configuration bits 3-2 LED5 00 01 10 11 LED control disabled 2 mA current source when P4.4 is configured as Quasi-bi-directional mode 4 mA current source when P4.4 is configured as Quasi-bi-directional mode 10 mA current source when P4.4 is configured as Quasi-bidirect. mode
Port LED0 Configuration bits 1-0 LED4 00 01 10 11 LED control disabled 2 mA current source when P4.3 is configured as Quasi-bi-directional mode 4 mA current source when P4.3 is configured as Quasi-bi-directional mode 10 mA current source when P4.3 is configured as Quasi-bidirect. mode
Reset Value = 0000 0000b 63
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Smart Card Interface Block (SCIB)
The SCIB provides all signals to interface directly with a smart card. The compliance with the ISO7816, EMV'2000, GSM and WHQL standards has been certified. Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. microprocessor card) are supported. The component supplies the different voltages requested by the smart card. The power off sequence is directly managed by the SCIB. The card presence switch of the smart card connector is used to detect card insertion or card removal. In case of card removal, the SCIB de-activates the smart card using the de-activation sequence. An interrupt can be generated when a card is inserted or removed. Any malfunction is reported to the microcontroller (interrupt + control register). The different operating modes are configured by internal registers. * * * * * * * * * * Support of ISO/IEC 7816 character mode one transmit/receive buffer 11 bits ETU counter 9 bits guard time counter 32 bits waiting time counter Auto character repetition on error signal detection in transmit mode Auto error signal generation on parity error detection in receive mode Power on and power off sequence generation Manual mode to drive directly the card I/O
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Block Diagram
The Smart Card Interface Block diagram is shown Figure 30: Figure 30. SCIB Block Diagram
Barrel shifter
IO (in)
Clk_iso
IO (out) CLK Etu counter Guard time counter Waiting time counter Scart fsm I/O mux RST C4 (out) C8 (out)
Clk_cpu
SCI Registers
C4 (in) C8 (in)
INT
Interrupt generator
Power on Power off fsm VCARD
Definitions
Terminal and ICC ETU T=0 T=1 Activation: Cold Reset Activation: Warm Reset De-Activation
This paragraph introduces some of the terms used in ISO 7816-3 and EMV recommendations. Please refer to the full recommendations for a complete list of terms. Terminal is the reader, ICC is the Integrated Circuit Card Elementary Timing Unit (Bit time) Character oriented half duplex protocol T=0 Block oriented half duplex protocol T=1 Reset initiated by the Terminal with Vcc power-up. The card will answer with ATR (see below) Reset initiated by the Terminal with Vcc already powered-up, and after a prior ATR or Warm Reset Deactivation by the Terminal as a result of : unresponsive ICC, or ICC removal.
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ATR F and D
Answer To Reset. Response from the ICC to a Reset initiated by the Terminal F = Clock Rate Conversion Factor, D = Bit rate adjustment factor. ETU is defined as : ETU = F/(D*f) with f = Card Clock frequency. If f is in Hertz, ETU is in second. F and D are available in the ATR (byte TA1). The default values are F=372, D=1. The time between 2 leading edges of the start bit of 2 consecutive characters is comprised of the character duration (10) plus the guard time. Be aware that the Guard Time counter and the Guard Time registers in the AT8xC5122/23 consider the time between 2 consecutive characters. So the equation is Guard Time Counter = Guard Time + 10. In other words, the Guard Time is the number of Stop Bits between 2 characters sent in the same direction. ISO IEC 7816-3 and EMV introduce the Extra Guard time to be added to the minimum Guard Time. Extra Guard Time only apply to consecutive characters sent by the terminal to the ICC. The TC1 byte in the ATR define the number N. For N=0 the character to character duration is 12 ETUs. For N=254 the character to character duration is 266. For N=255 (special case) The minimum character to character duration is to be used : 12 for T=0 protocol and 11 for T=1 protocol.
Guard Time
Extra Guard Time
Block Guard Time Work Waiting Time (WWT)
The time between the leading edges of 2 consecutive characters sent in opposit direction. ISO IEC 7816-3 and EMV recommend a fixed Block Guard Time of 22 ETUs. In T=0 protocol WWT is the interval between the leading edge of any character sent by the ICC, and the leading edge of the previous character sent either by the ICC or the Terminal. If no character is received by the terminal after WWTmax time, the Terminal initiates a De-Activation Sequence.
Character Waiting Time (CWT) In T=1 protocol CWT is the interval between the leading edge of 2 consecutive characters sent by the ICC. If the next character is not received by the Terminal after CWTmax time, the Terminal initiates a De-Activation Sequence. Block Waiting Time (BWT) In T=1 protocol BWT is the interval between the leading edge of the start bit of the last character sent by the Terminal that gives the right to sent to the ICC, and the leading edge of the start bit of the first character sent by the ICC. If the first character from the ICC is not received by the Terminal after BWTmax time, the Terminal initiates a De-Activation Sequence. In T=1 protocol the ICC can request a Waiting Time Extension with a S(WTX request) request. The Terminal should acknowlege it. The Waiting time between the leading edge of the start bit of the last character sent by the Terminal that gives the right to sent to the ICC, and the leading edge of the start bit of the first character sent by the ICC will be BWT*WTX ETUs. In T=0 protocol, a Terminal (respectively an ICC) detecting a parity error while receiving a character shall force the Card IO line at 0 starting at 10.5 ETUs, thus reducing the first Guard bit by half the time. The Terminal (respectively an ICC) shall maintain a 0 for 1 ETU min and 2 ETUs max (according to ISO IEC) or to 2 ETUs (according to EMV). The ICC (respectively a Terminal) shall monitor the Card IO to detect this error signal then attempt to repeat the character. According to EMV, following a parity error the character can be repeated one time, if parity error is detected again this procedure can be repeated 3 more times. The same character can be transmitted 5 times in total. ISO
Waiting Time Extention (WTX)
Parity error in T=0 protocol
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IEC7816-3 says this procedure is mandatory in ATR for card supporting T=0 while EMV says this procedure is mandatory for T=0 but does not apply for ATR.
Functional Description
Barrel Shifter
The architecture of the Smart Card Interface Block can be detailed as follows: The Barrel Shifter performs the translation between 1 bit serial data and 8 bits parallel data The barrel function is useful for character repetition since the character is still present in the shifter at the end of the character transmission. This shifter is able to shift the data in both directions and to invert the input or output value in order to manage both direct and inverse ISO7816-3 convention. Coupled with the barrel shifter is a parity checker and generator. There are 2 registers connected to this barrel shifter, one for the transmission and one for the reception. They act as buffers to relieve the CPU of timing constraints.
SCART FSM
(Smart Card Asynchronous Receiver Transmitter Finite State Machine) This is the core of the block. Its purpose is to control the barrel shifter. To sequence correctly the barrel shifter for a reception or a transmission, it uses the signals issued by the different counters. One of the most important counters is the guard time counter that gives time slots corresponding to the character frame. The SCART FSM is enabled only in UART mode. The transition from the receipt mode to the transmit mode is done automatically. Priority is given to the transmission. Transmission refers to Terminal transmission to the ICC. Reception refers to reception by the Terminal from the ICC.
ETU Counter
The ETU (Elementary Timing Unit) counter controls the working frequency of the barrel shifter, in fact it generates the enable signal of the barrel shifter. It receives the Card Clock, and generates the ETU clock. The Card Clock frequency is called "f" below. The ETU counter is 11 bit wide. A special compensation mode can be activated. It accomodates situations where the ETU is not an integer number of Card Clock (CK_ISO). The compensation mode is controlled by the COMP bit in SCETU1 register bit position 7. With COMP=1 the ETU of every character even bits is reduced by 1 Card Clock period. As a result, the average ETU is : ETU_average = (ETU - 0.5). One should bear in mind that the ETU counter should be programmed to deliver a faster ETU which will be reduced by the COMP mechanism, not the other way around. This allows to reach the required precision of the character duration specified by the ISO7816-3 standard. Example1 : F=372, D=32 => ETU= F/D = 11.625 clock cycles. We select ETU[10-0] = 12 , COMP=1. ETUaverage= 12 - (0.5*COMP) = 11.5 The result will be a full character duration (10 bit) = (10 - 0.107)*ETU. The EMV specification is (10 +/- 0.2)*ETU
Guard Time Counter
The minimum time between the leading edge of the start bit of 2 consecutive characters transmitted by the Terminal is controlled by the Guard Time counter, as described in Figure 33.
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The Guard Time counter is an 9 bit counter It is initialized at 001h at the start of a transmission by the Terminal. It then increments itself at each ETU until it reach the 9 bit value loaded into the SCGT1[0] concatenated with SCGT0[7:0]. At this time a new Terminal transmission is enabled and the Guard Time Counter stop incrementing. As soon as a new transmission start, the Guard Time Counter is re-initialized at 1 decimal value. It should be noted that the value of the Guard Time Counter cannot be red. Reading SCGT1,0 only gives the minimum time between 2 characters that the Guard Time Counter will allow. Care must be taken with the Guard Time Counter which counts the duration between the leading edges of 2 consecutive characters. This correspond to the character duration (10 ETU) plus the Guard Time as defined by the ISO and EMV recommendations. To program Guard Time = 2 : 2 stop bits between 2 characters which is equivalent to the minimum delay of 12 ETUs between the leading edges of 2 consecutive characters, SCGT1[0],SCGT0[7:0] should be loaded with the value 12 decimal. See Figure 31 Figure 31. Guard Time. TRANSMISSION to ICC
CHAR n+1
CHAR n+2
CHAR n+3
>= SCGT
Block Guard Time Counter
The Block Guard Time counter provides a way to program a minimum time between the leading edge of the start bit of a character received from the ICC and the leading edge of the start bit of a character sent by the terminal. ISO IEC 7816-3 and EMV recommend a fixed Block Guard Time of 22 ETUs. The AT8xC5122/23 offer the possibility to extend this delay up to 512 ETUs. The Block Guard Time is a 9 bit counter. When the Block Guard Time mode is enabled (BGTEN=1 in SCSR register) The Block Guard Time counter is initialized at 000h at the start of each character transmissions from the ICC. It then increments at each ETU until it reach the 9 bit value loaded into shadow SCGT1,0 registers, or until it is re-initialized by the start of an new transmission from the ICC. If the Block Guard Time counter reaches the 9 bit value loaded into shadow SCGT1,0 registers, a transmission by the TERMINAL is enabled, and the Block Guard Time counter stop incrementing. The Block Guard Time counter is re-initialized at the start of each TERMINAL transmission. The SCGT1 SCGT0 shadow registers are loaded with the content of GT[8-0] contained in the registers SCGT1[0),SCGT0(7:0] with the rising edge of the bit BGTEN in the SCSR register. See Figure 33.
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Figure 32. Block Guard Time. RECEPTION from ICC
Write SCGT1,0 with a value for Guard Time CHAR 1 CHAR 2 CHAR n CHAR n+1 CHAR n+2 CHAR n+3
TRANSMISSION to ICC
>= SCGT >= Block Guard Time
Write "Block Guard Time" in SCGT1,0 and set BGTEN to transfer the value to the shadow SCGT1,0 registers
Figure 33. Guard Time and Block Guard Time counters
ETU Counter
Guard Time Counter 9 bits Enable transmit Comparator 9 bits 9 bits
Block Guard Time Counter 9 bits Comparator Enable transmit
Shadow SCGT1 ,Shadow SCGT0 GT[8:0] SCGT1 SCGT0
To illustrate the use of Guard Time and Block Guard Time, let us consider the ISO/IEC7816-3 recommendation : Guard Time = 2 (minimum delay between 2 consecutive characters sent by the Terminal = 12 ETUs), and Block Guard Time = 22 ETUs. After A smart Card Reset - - - Write 00decimal in SCGT1, Write 21decimal in SCGT0 Set BGTEN in SCSR (BGTEN was 0 before as a result of the smart card reset) Write 12decimal in SCGT0
Now the Guard Time and Block Guard Time are properly initialized. The TERMINAL will insure a minimun 12 ETUs between 2 leading edges of 2 consecutive characters transmitted. The TERMINAL will also insure a minimum of 22 ETUs between the leading edge of a character sent by the ICC, and the leading edge of a character sent by the TERMINAL. There is no need to write SCGT1,0 again and again.
Waiting Time (WT) Counter
The WT counter is a 32 bits down counter which can be loaded with the value contained in the SCWT3, SCWT2, SCWT1, SCWT0 registers. Its main purpose is timeout signal generation. It is 32 bits wide and is decremented at the ETU rate. see Figure 34. 69
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When the WT counter times out, an interrupt is generated and the SCIB function is locked: reception and emission are disabled. It can be enabled by resetting the macro or reloading the counter. The Waiting Time Counter can be used in T=0 protocol for the Work Waiting Time. It can be used in T=1 protocol for the Character Waiting Time and for the Block Waiting Time. See the detailed explanation below. Figure 34. Waiting Time Counter
ETU Counter WTEN Write_SCWT2 UART Start Bit
WT Counter Load WT[31:0] SCWT3 SCWT2 SCWT1 SCWT0 Timeout
In the so called manuel mode, the counter is loaded, if WTEN = 0, during the write of SCWT2 register. The counter is loaded with a 32 bit word built with SCWT3 SCWT2 SCWT1 SCWT0 registers (SCWT0 contain WT[7-0] byte. WTEN is located in the SCICR register. When WTEN=1 and in UART mode, the counter is re-loaded at the occurence of a start bit. This mode will be detailed below in T=0 protocol and T=1 protocol. In manual mode, the WTEN signal controls the start of the counter (rising edge) and the stop of the counter (falling edge). After a timeout of the counter, a falling edge on WTEN, a reload of SCWT2 and a rising edge of WTEN are necessary to start again the counter and to release the SCIB macro. The reload of SCWT2 transfers all SCWT0, SCWT1, SCWT2 and SCWT3 registers to the WT counter. In UART mode there is an automatic load on the start bit detection. This automatic load is very useful for changing on-the-fly the timeout value since there is a register to hold the load value. This is the case for T=1 protocol. In T=0 protocol the maximun interval between the start leading edge of any character sent by the ICC and the start of the previous character sent by either the ICC or the Terminal is the maximum Work Waiting Time. The Work Waiting Time shall not exceed 960*D*WI ETUs with D and WI parameters are returned by the field TA1 and TC2 respectively in the Answer To Reset (ATR). This is the value the user shall write in the SCWT0,1,2,3 register. This value will be reloaded in the Waiting Time counter every start bit.
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Figure 35. T=0 mode
> GT CHAR 1 CHAR 2
< WT
In T=1 protocol : The maximum interval between the leading edge of the start bit of 2 consecutive characters sent by the ICC is called maximum Character Waiting Time. The Character Waiting Time shall not exceed (2**CWI + 11) ETUs with 0 =< BWI =< 5. Consequently 12 ETUs =< CWT =< 43 ETUs. T=1 protocol also specify the maximum Block Waiting Time. This is the time between the leading edge of the last character sent by the Terminal giving the right to send to the ICC, and the leading edge of the start bit of the first character sent by the ICC. The Block Waiting Time shall not exceed (2**BWI*960 + 11) ETUs with 0 =< BWI =< 4. Consequently 971 ETUs =< BWT =< 15371 ETUs. In T=1 protocol it is possible to extend the Block Waiting Time with the Waiting Time Extension (WTX). When selected the waiting time becomes BWT*WTX ETUs. The Waiting Time counter is 32 bit wide to accomodate this feature. It is possible to take advantage of the automatic reload of the Waiting Time counter with a start bit in UART mode (T=1 protocol use UART mode) . If the Terminal sends a block of N characters, and the ICC is supposed to respond immediately after, then the following sequence can be used. While sending the (N-1)th character of the block, the Terminal can write the SCWT0,1,2,3 with BWImax. At the start bit of the Nth character, the BWImax is loaded in the Waiting Time counter During the transmission of the Nth character, the Terminal can write SCWT0,1,2,3 with the CWImax. At the start bit of the first character sent by the ICC, the CWImax will be loaded in the Waiting Time counter.
Figure 36. T=1 Mode TRANSMISSION
BLOC 1 CHAR 1 CHAR 2 CHAR n CHAR n+1
RECEPTION
BLOC 2 CHAR n+2 CHAR n+3
< BWT
< CWT
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Power-on and Power-off FSM
The Power-on Power-off Finite State Machine (FSM) applies the signals on the smart card in accordance with ISO7816-3 standard. It conducts the Activation (Cold Reset and Warm Reset as well as De-Activation) it also manages the exception conditions such as overcurrent (see DC/DC Converter) To be able to power on the SCIB, the card presence is mandatory. Upon detectection of a card presence, the Terminal initiate a Cold Reset Activation. The Cold Reset Activation Terminal procedure is as follow and the Figure 37. Timing indications are given according to ISO IEC 7816 - - - - - RESET= Low , I/O in the receive state Power Vcc (see DC/DC Converter) Once Vcc is established, apply Clock at time Ta Maintain Reset Low until time Ta+tb (tb< 400 clocks) Monitor The I/O line for the Answer To Reset (ATR) between 400 and 40000 clock cycles after Tb. ( 400 clocks < tc < 40000clocks)
Figure 37. SCIB Activation Cold Reset Sequence after a Card Insertion
CVCC CRST CCLK CIO
Undefined Ta Ta+tb Data Tb+tc
The Warm Reset Activation Terminal procedure is as follow and the Figure 38 - - - - - Vcc active, Reset = High, CLK active Terminal drive Reset low at time T to initiate the warm Reset. Reset=0 maintained for at least 400 clocks until time Td = T+te (400 clocks < te) Terminal keep the IO line in receive state Terminal drive Reset high after at least 400 clocks at time Td ICC shall respond with an ATR within 40000 clocks (tf<40000 clocks)
Figure 38. SCIB Activation Warm Reset Sequence
CVCC CRST CCLK CIO
Undefined T Td=T + te Data Td + tf
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Removal of the smart card will automatically start the power off sequence as described in Figure 39. The SCIB deactivation sequence after a reset of the CPU or after a lost of power supply is ISO7816-3 compliant. The switching order of the signals is the same as in Figure 39 but the delay between signals is analog and not clock dependant. Figure 39. SCIB Deactivation Sequence after a Card Extraction CVCC CRST CCLK CIO 8 Clock Cycles
Interrupt Generator
There are several sources of interruption but the SCIB macro-cell issues only one interrupt signal: SCIBIT. Figure 40. SCIB Interrupt Sources
Transmit buffer copied to shift register Output current out of range Output voltage out of range Timeout on WT counter Complete transmission Complete reception Parity error detected SCTBI ESCTBI ICARDERR ICARDER VCARDERR EVCARDER SCWTI ESCWTI SCTI ESCTI SCRI ESCRI SCPI ESCPI
SCIB IT
This signal is high level active. Each of the sources is able to activate the SCIB interruption which is cleared when the Smart Card Interrupt register is read by the microcontroller. If during the read of the Smart Card Interrupt register another interrupt occurs, the activation of the corresponding bit in the Smart Card Interrupt register and the new SCIB interruption is delayed until the interrupt register is read by the microcontroller.
Warning : Each bit of the SCIIR register is irrelevant while the corresponding interruption is disabled in SCIER register. When the interruption mode is not used, the bits of the SCISR register must be used instead of the bits of the SCIIR register.
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Additional Features
Clock The CK_ISO input must be in the range 1 - 5 MHz according to ISO 7816. The CK_ISO can be programmed up to 12 MHz. In this case, the timing specification of the output buffer will not comply to ISO 7816. Figure 41. Clock Diagram of the SCIB Block
CK_IDLE Ck_cpu
CK_PLL or CK_XTAL1
PR2
Ck_ISO SCIB
Figure 42. Prescaler 2 Description
PR2 0 1/(2*(48 - SCICLK[5-0]))
<48 =48
CK_PLL
CK_XTAL1 1
CK_ISO
XTSCS EXT48
SCICLK.7
SCICLK[5:0]
PLLCON.2
The division factor SCICLK must be smaller than 49. If it is greater or equal to 49, the PR2 prescaler is locked. See Figure 17 clock tree diagram in the clock controller chapter. Table 42. Examples of Clock settings
XTAL1 (MHz) 8 8 8 8 8 8 EXT48 0 0 0 0 0 0 SCICLK 36 44 42 40 24 0 CK_ ISO 4 12 8 6 2 1
Card Presence Input
The internal pull-up (weak pull-up) on Card Presence input can be disconnected in order to reduce the consumption (CPRESRES, bit 3 in PMOD0). In this case, an external resistor (typically 1 M) must be externally tied to Vcc. CPRES input can generate an interrupt (see Interrupt system section). The detection level can be selected.
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Transmit / Receive Buffer The contents of the SCIBUF Transmit / Receive Buffer is transferred or received into / from the Shift Register. The Shift Register is not accessible by microcontroller. Its role is to prepare the byte to be copied on the I/O pin for a transmission or in the SCIBUF buffer after a reception. During a character transmission process, as soon as the contents of the SCIBUF buffer is transferred to the shift register, the SCTBE bit is set in SCISR register to indicate that the SCIBUF buffer is empty and ready to accept a new byte. This mechanism avoids to wait for the complete transmission of the previous byte before writing a new byte in the buffer and enables to speed up the transmission. - If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the contents of the Shift Register is transferred to I/O pin, the SCTC bit is set in SCISR register to indicate that the byte has been transmitted. If the Character repetition mode is selected (bit CREP=1 in SCICR) The TERMINAL will be able to repeat characters as requested by the ICC (See the Parity Error in T=0 protocol description in the definition paragraph above). The SCTC bit in SCISR register will be set after a successful transmission (no retry or no further retry requested by the ICC). If the number of retries is exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last retry is still unsuccessful, the SCTC bit in SCISR will not be set and the SCPE bit in SCISR register will be set instead.
-
During a character reception process, the contents of the Shift Register is transferred in the SCIBUF buffer. - If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the contents of the Shift Register is transferred to the SCIBUF the SCRC bit is set in SCISR register to indicate that the byte has been received, and the SCIBUF contains a valid character ready to be red by the microcontroller. If the Character repetition mode is selected (bit CREP=1 in SCICR) The TERMINAL will be able to request repetition if the received character exhibit a parity error. Up to 4 retries can be requested depending on CREPSEL bit in SCSR. The SCRC bit will be set in SCISR register after a successful reception, first reception or after retry(ies). If the number of retries is exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last retry is still unsuccessful, the SCRC bit and the SCPE bit in SCISR register will be set. It will be possible to read the erroneous character.
-
Warning : the SCTBI, SCTI SCRI and SCPI bits have the same function as SCTBE, SCTC, SCRC and SCPE bits. The first ones are able to generate interruptions if the interruptions are enabled in SCIER register while the second ones are only status bits to be used in pulling mode. If the interruption mode is not used, the status bits must be used. The SCTBI, SCTI and SCRI bits do not contain valid information while their respective interrupt enable bits ESCTBI, EXCTI, ESCRI are cleared.
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Figure 43. CharacterTransmission Diagram SCISR register
SCTBE SCTC SCPE
Transmitted Character
SCIBUF
Shift Register I/O pin
ESCTBI SCIER Register
Parity error
ESCTI
Parity error
SCTBI
SCTI
SCPI
SCIIR register
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Figure 44. Character Reception Diagram SCISR register
SCTBE SCTC SCRC SCPE
Shift Register I/O pin
SCIBUF
Parity error
Received Character
ESCTBI SCIER Register
ESCTI ESCRI
Parity error
SCTBI
SCTI
SCRI
SCPI
SCIIR register
SCIB Reset
The SCICR register contains a reset bit. If set, this bit generates a reset of the SCIB and its registers. Table 43 defines the SCIB registers that are reset and their reset values. Table 43. Reset Values for SCI Registers
Register Name SCICR SCCON SCISR SCIIR SCIER SCSR SCIBUF SCETU1, SCETU0 SCGT1, SCGT0 SCWT3, SCWT2, SCWT1, SCWT0 SCICLK
SCIB Reset Value (Binary) 0000 0000 0X00 0000 1000 0000 0X00 0000 0X00 0000 X000 1000 0000 0000 XXXX X001, 0111 0100 (372) 0000 0000, 0000 1100 (12) 0000 0000, 0000 0000, 0010 0101, 1000 0000 (9600) 0X10 1111
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Alternate Card
A second card named `Alternate Card' can be controlled. The Clock signal CCLK1 can be adapted to the XTAL frequency. Thanks to the clock prescaler which can divide the frequency by 1, 2, 4 or 8. The bits ALTKPS0 and ALTKPS1 in SCSR Register are used to set this factor. Figure 45. Alternate Card
CVCC CRST CIO CCLK CPRES CK_IDLE 1, 1/2, 1/4 or 1/8 P1.7 1 0 SCCLK1 SCSR Reg. SIM, SAM CARD SMART CARD Main card
PR3
CCLK1
Alternate card
ALTKPS0,1 SCSR Reg.
Registers
There are fifteen registers to control the SCIB macro-cell. They are described from Table 58 to Table 45. Some of the register widths are greater than a byte. Despite the 8 bits access provided by the BIU, the address mapping of this kind of register respects the following rule : The Low significant byte register is implemented at the higher address. This implementation makes access to these registers easier when using high level programming languages (C,C++).
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Table 44. Smart Card Interface Control Register - SCICR (S:B6h, SCRS = 1)
7 RESET Bit Number 6 CARDDET Bit Mnemonic 5 VCARD1 Description Reset Set this bit to reset and deactivate the Smart Card Interface. Clear this bit to activate the Smart Card Interface. This bit acts as an active high software reset. 6 CARDDET Card Presence Detector Sense Clear this bit to indicate the card presence detector is open when no card is inserted (CPRES is high). Set this bit to indicate the card presence detector is closed when no card is inserted (CPRES is low). Card Voltage Selection: VCARD[1] VCARD[0] 5-4 VCARD[1:0] 0 0 1 1 0 1 0 1 CVCC 0V 1.8 V 3.0 V 5.0 V 4 VCARD0 3 UART 2 WTEN 1 CREP 0 CONV
7
RESET
3
UART
Card UART Selection Clear this bit to use the CARDIO bit (P1.0) bit to drive the Card I/O (P1.0) pin. Set this bit to use the Smart Card UART to drive the Card I/O pin (P1.0 pin). Controls also the Waiting Time Counter as described in Section "Waiting Time (WT) Counter", page 69 Waiting Time Counter Enable Clear this bit to stop the counter and enable the load of the Waiting Time counter hold registers.
2
WTEN
The hold registers are loaded with SCWT0, SCWT1, SCWT2 and SCWT3 values when SCWT2 is written. Set this bit to start the Waiting Time Counter. The counters stop when it reaches the timeout value. If the UART bit is set, the Waiting Time Counter automatically reloads with the hold registers whenever a start bit is sent or received. Character Repetition Clear this bit to disable parity error detection and indication on the Card I/O pin in receive mode and to disable character repetition in transmit mode. Set this bit to enable parity error indication on the Card I/O pin in receive mode and to set automatic character repetition when a parity error is indicated in transmit mode.
1
CREP
Depending upon CREPSET bit is SCSR register, the receiver can indicate parity error up to 4times (3 repetitions) or up to 5times (4 repetitions) after which it will raise the parity error bit SCPE bit in the SCISR register. If parity interrupt is enabled, the SCPI bit in SCIIR register will be set too. Alternately, the transmitter will detect ICC character repetition request. After 3 or 4 unsuccessful repetitions (depending on CREPSEL bit in SCSR register), the transmitter will raise the parity error bit SCPE bit in the SCISR register. If parity interrupt is enabled, the SCPI bit in SCIIR register will be set too. Note : Character repetition mode is specified for T=0 protocol only and should not be used in T=1 protocol (block oriented protocol) ISO Convention Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the parity bit is added after b7 bit and a low level on the Card I/O pin represents a'0'. Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity bit is added after b0 bit and a low level on the Card I/O pin represents a'1'.
0
CONV
Reset Value = 0000 0000b
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Table 45. Smart Card Contacts Register - SCCON (S:ACh, SCRS=0)
7 CLK Bit Number 6 Bit Mnemonic 5 CARDC8 Description Card Clock Selection Clear this bit to use the Card CLK bit (CARDCLK bit below) to drive Card CLK (P1.4) pin. Set this bit to use CK_XTAL1 or CK_PLL signals for CK_ISO to drive the Card CLK pin (CCLK = P1.4 pin) Note: internal synchronization avoids glitches on the CLK pin when switching this bit. 6 Reserved This bit can be changed by software but the read value is indeterminate. Card C8 Clear this bit to drive a low level on the Card C8 pin (CC8 = P1.1 pin). Set this bit to set a high level on the Card C8 pin (CC8 = P1.1 pin).. The CC8 pin can be used as a pseudo bi-directional I/O when this bit is set. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of CC8 pin Card C4 Clear this bit to drive a low level on the Card C4 pin (CC4 = P1.3 pin). Set this bit to set a high level on the Card C4 pin (CC4 = P1.3 pin). The CC4 pin can be used as a pseudo bi-directional I/O when this bit is set. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of CC4 pin Card I/O If UART bit is cleared in SCICR register, this bit enables the use of the Card IO pin (CIO = P1.0) as a C51 pseudo bi-directional port : 3 CARDIO To read from CIO (P1.0) port pin : set CARDIO (P1.0) bit then read CARDIO (P1.0) bit to have the CIO port value To write in CIO (P1.0) port pin : set CARDIO (P1.0) bit to write a 1 in CIO (P1.0) port pin , clear CARDIO (P1.0) bit to write a 0 in CIO (P1.0) port pin. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of CIO pin Card CLK When the CLK bit is cleared in SCCON Register, the value of this bit is driven to the Card CLK pin. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of Card CLK pin Card RST Clear this bit to drive a low level on the Card RST pin. Set this bit to set a high level on the Card RST pin. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of Card RST pin Card VCC Control Clear this bit to desactivate the Card interface and set its power-off. The other bits of SCCON register have no effect while this bit is cleared. Set this bit to power-on the Card interface. The activation sequence should be handled by software. 4 CARDC4 3 CARDIO 2 CARDCLK 1 CARDRST 0 CARDVCC
7
CLK
5
CARDC8
4
CARDC4
2
CARDCLK
1
CARDRST
0
CARDVCC
Reset Value = 0X00 0000b
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Table 46. Smart Card UART Interface Status Register SCISR (S:ADh, SCRS=0)
7 SCTBE Bit Number 6 CARDIN Bit Mnemonic 5 ICARDOVF Description UART Transmit Buffer Empty Status This bit is set by hardware when the Transmit Buffer is copied to the transmit shift register of the Smart Card UART. It is cleared by hardware when SCIBUF register is written. Card Presence Status This bit is set by hardware if there is a card presence (debouncing filter has to be done by software). This bit is cleared by hardware if there is no card presence. Card Current Overflow Status 5 ICARDOVF This bit is set when the current on card is above the limit specified by bit OVFADJ in DCCKPS register (Table 61 on page 94) It is cleared by hardware. Card Voltage Correct Status This bit is set when the output voltage is within the voltage range specified by VCARD[1:0] in SCICR register. It is cleared otherwise. Waiting Time Counter Timeout Status This bit is set by hardware when the Waiting Time Counter has expired. It is cleared by the reload of the counter or by the reset of the SCIB. UART Transmitted Character Status This bit is set by hardware when the Smart Card UART has transmitted a character. If character repetition mode is selected, this bit will be set only after a successful transmission. If the last allowed repetition in not successful, this bit will not be set. It is cleared by software when this register is read. UART Received Character Status This bit is set by hardware when the Smart Card UART has received a character It is cleared by hardware when SCIBUF register is read. If character repetition mode is selected, this bit will be set only after a successful reception. If the last allowed repetition is still unsuccessful, this bit will be set to let the user read the erroneous value if necessary. Character Reception Parity Error Status This bit is set when a parity error is detected on the received character. It is cleared by software when this register is read. If character repetition mode is selected, this bit will be set only if the ICC report an error on the last allowed repetition of a TERMINAL transmission, or if a reception parity error is found on the last allowed ICC character repetition. 4 VCARDOK 3 SCWTO 2 SCTC 1 SCRC 0 SCPE
7
SCTBE
6
CARDIN
4
VCARDOK
3
SCWTO
2
SCTC
1
SCRC
0
SCPE
Reset Value = 1000 0000b
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Table 47. Smart Card UART Interrupt Identification Register (Read Only) SCIIR (S:AEh, SCRS=0)
7 SCTBI Bit Number 6 5 ICARDERR Description UART Transmit Buffer Empty Interrupt This bit is set by hardware when the Transmit Buffer is copied into the transmit shift register of the Smart Card UART. It generates an interrupt if ESCTBI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. Reserved The value read from this bit is indeterminate. Do not change this bit. Card Current Overflow Interrupt 5 ICARDERR This bit is set when the current on card is above the limit specified by bit OVFADJ in DCCKPS register (Table 61 on page 94). It generates an interrupt if ICARDER bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. Card Voltage Error Interrupt This bit is set when the output voltage goes out of the voltage range specified by VCARD field. It generates an interrupt if EVCARDER bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. Waiting Time Counter Timeout Interrupt This bit is set by hardware when the Waiting Time Counter has expired. It generates an interrupt if ESCWTI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. UART Transmitted Character Interrupt This bit is set by hardware when the Smart Card UART has completed the character transmission. It generates an interrupt if ESCTI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. UART Received Character Interrupt This bit is set by hardware when the Smart Card UART has completed the character reception. It generates an interrupt if ESCRI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. Character Reception Parity Error Interrupt This bit is set at the same time as SCTI or SCRI if a parity error is detected on the received character. It generates an interrupt if ESCPI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. 4 VCARDERR 3 SCWTI 2 SCTI 1 SCRI 0 SCPI
Bit Mnemonic
7
SCTBI
6
-
4
VCARDERR
3
SCWTI
2
SCTI
1
SCRI
0
SCPI
Reset Value = 0X00 0000b
Note: 1) In case of multiple interrupts occuring at the same time (sampled by the same edge of the internal clock), the interrupts will be serviced in the following order from the highest to the lowest priority : - UART Transmit Buffer Empty - Card Current Overflow - Card Voltage Error - Waiting Time Counter Timeout - UART Transmitted Character - UART Received Character - Character Reception Parity Error 2) It is recommended that the application saves the SCIIR register after reading it in order to avoid the loss of pending interruptions as the SCIIR register is cleared when it is read by the MCU.
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Table 48. Smart Card UART Interrupt Enabling Register - SCIER (S:AEh, SCRS=1)
7 ESCTBI Bit Number 7 6 Bit Mnemonic ESCTBI 5 ICARDER Description UART Transmit Buffer Empty Interrupt Enabled Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt. Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt. Reserved The value read from this bit is indeterminate. Do not change this bit. Card Current Overflow Interrupt Enabled Clear this bit to disable the Card Current Overflow interrupt. Set this bit to enable the Card Current Overflow interrupt. Card Voltage Error Interrupt Enabled Clear this bit to disable the Card Voltage Error interrupt. Set this bit to enable the Card Voltage Error interrupt. WaitingTime Counter Timeout Interrupt Enabled Clear this bit to disable the Waiting Time Counter timeout interrupt. Set this bit to enable the Waiting Time Counter timeout interrupt. UART Transmitted Character Interrupt Enabled Clear this bit to disable the Smart Card UART Transmitted Character interrupt. Set this bit to enable the Smart Card UART Transmitted Character interrupt. UART Received Character Interrupt Enabled Clear this bit to disable the Smart Card UART Received Character interrupt. Set this bit to enable the Smart Card UART Received Character interrupt. Character Reception Parity Error Interrupt Enabled Clear this bit to disable the Smart Card Character Reception Parity Error interrupt. Set this bit to enable the Smart Card Character Reception Parity Error interrupt. 4 EVCARDER 3 ESCWTI 2 ESCTI 1 ESCRI 0 ESCPI
6
-
5
ICARDER
4
EVCARDER
3
ESCWTI
2
ESCTI
1
ESCRI
0
ESCPI
Reset Value = 0X00 0000b
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Table 49. Smart Card Selection Register - SCSR (S:ABh)
7 Bit Number 7 6 BGTEN Bit Mnemonic 5 Description Reserved The value read from this bit is indeterminate. Do not change this bit. Block Guard Time Enable 6 BGTEN Set this bit to select the minimum interval between the leading edge of the start bits of the last character received from the ICC and the first character sent by the Terminal. The transfer of GT[8-0] value to the BGT counter is done on the rising edge of the BGTEN. Clear this bit to suppress the minimum time between reception and transmission. 5 Reserved The value read from this bit is indeterminate. Do not change this bit. Character repetition selection 4 CREPSEL Clear this bit to select 5 times transmission (1 original + 4 repetitions) before parity error indication (conform to EMV) Set this bit to select 4 times transmission (1 original + 3 repetitions) before parity error indication Alternate Card Clock prescaler factor 00 ALTKPS = 0: prescaler factor equals 1 3-2 ALTKPS1:0 01 ALTKPS = 1: prescaler factor equals 2 10 ALTKPS = 2: prescaler factor equals 4 (reset value) 11 ALTKPS = 3: prescaler factor equals 8 Alternate card clock selection 1 SCCLK1 Set to select the prescaled PR3 clock for CCLK1 (P1.7) pin Clear to select P1.7 port bit 0 SCRS Smart Card Register Selection The SCRS bit selects which set of the SCIB registers is accessed. 4 CREPSEL 3 ALTKPS1 2 ALTKPS0 1 SCCLK1 0 SCRS
Reset Value = X000 1000b Table 50. Smart Card Transmit / Receive Buffer - SCIBUF (S:AA)
7 Bit Number 6 Bit Mnemonic 5 Description Smart Card Transmit / Receive Buffer - A new byte can be written in the buffer to be transmitted on the I/O pin when SCTBE bit is set. The bits are sorted and copied on the I/O pin versus the active convention. - A new byte received from I/O pin is ready to be read when SCRI bit is set. The bits are sorted versus the active convention. 4 3 2 1 0 -
Reset Value = 0000 0000b
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Table 51. Smart Card ETU Register 1 - SCETU1 (S:ADh, SCRS=1)
7 COMP Bit Number 6 Bit Mnemonic 5 Description Compensation Clear this bit when no time compensation is needed (i.e. when the ETU to Card CLK period ratio is close to an integer with an error less than 1/4 of Card CLK period). Set this bit otherwise and reduce the ETU period by 1 Card CLK cycle for even bits. Reserved The value read from these bits is indeterminate. Do not change these bits. ETU MSB Used together with the ETU LSB in SCETU0 (Table 52) 2-0 ETU[10:8] Warning : the ETU counter is reloaded at each register's write operation. Do not change this register during character reception or transmission or while Guard Time or Waiting Time Counters are running. 4 3 2 ETU10 1 ETU9 0 ETU8
7
COMP
6-3
-
Reset Value = 0XXX X001b Table 52. Smart Card ETU Register 0 - SCETU0 (S:ACh, SCRS=1)
7 ETU7 Bit Number 6 ETU6 Bit Mnemonic 5 ETU5 Description ETU LSB The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK frequency. According to ISO 7816, ETU[10:0] can be set between 11 and 2048 (2047 ?) The default reset value of ETU[10:0] is 372 (F=372, D=1). 4 ETU4 3 ETU3 2 ETU2 1 ETU1 0 ETU0
7-0
ETU[7:0]
Reset Value = 0111 0100b
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Table 53. Smart Card Transmit Guard Time Register 0 - SCGT0 (S:B4h, SCRS=1)
7 GT7 Bit Number 6 GT6 Bit Mnemonic 5 GT5 Description Transmit Guard Time LSB The minimum time between two consecutive start bits in transmit mode is GT[8:0] * ETU. This is equal to ISO IEC Guard Time +10 (see Guard Time Counter description. According to ISO IEC 7816,the time between 2 consecutive leading edge start bits can be set between 11 and 266 (11 to 254+12 ETUs). 4 GT4 3 GT3 2 GT2 1 GT1 0 GT0
7-0
GT[7:0]
Reset Value = 0000 1100b Table 54. Smart Card Transmit Guard Time Register 1 - SCGT1 (S:B5h, SCRS=1)
7 Bit Number 7-1 0 6 Bit Mnemonic GT8 5 Description Reserved The value read from these bits is indeterminate. Do not change these bits. Transmit Guard Time MSB Used together with the Transmit Guard Time LSB in SCGT0 register (Table 53). 4 3 2 1 0 GT8
Reset Value = XXXX XXX0b Table 55. Smart Card Character/Block Waiting Time Register 3 SCWT3 (S:C1h, SCRS=0)
7 WT31 Bit Number 7-0 6 WT30 Bit Mnemonic WT[31:24] 5 WT29 Description Waiting Time Byte3 Used together with WT[23:0] in registers SCWT2,SCWT1, SCWT0 (see Table 56). 4 WT28 3 WT27 2 WT26 1 WT25 0 WT24
Reset Value = 0000 0000b
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Table 56. Smart Card Character/Block Waiting Time Register 2 SCWT2 (S:B6h, SCRS=0)
7 WT23 Bit Number 7-0 6 WT22 Bit Mnemonic WT[23:16] 5 WT21 Description Waiting Time Byte2 Used together with WT[31:24] and WT[15:0] in registers SCWT3,SCWT1, SCWT0 (see Table 58). 4 WT20 3 WT19 2 WT18 1 WT17 0 WT16
Reset Value = 0000 0000b Table 57. Smart Card Character/Block Waiting Time Register 1 SCWT1 (S:B5h, SCRS=0)
7 WT15 Bit Number 7-0 6 WT14 Bit Mnemonic WT[15:8] 5 WT13 Description Waiting Time Byte 1 Used together with WT[31:16] and WT[7:0] in registers SCWT3,SCWT2, SCWT0 (see Table 55). 4 WT12 3 WT11 2 WT10 1 WT9 0 WT8
Reset Value = 0010 0101b Table 58. Smart Card Character/Block Waiting Time Register 0 SCWT0 (S:B4h, SCRS=0)
7 WT7 Bit Number 6 WT6 Bit Mnemonic 5 WT5 Description Waiting Time Byte 0 7-0 WT[7:0] WT[31:0] is the reload value of the Waiting Time Counter (WTC). The WTC is a general-purpose timer. It is using the ETU clock and is controlled by the WTEN bit (see Table 44 on page 79 and Section "Waiting Time (WT) Counter", page 69). When UART bit of Registers is set, the WTC is automatically reloaded at each start bit of the UART. It is used to check the maximum time between to consecutive start bits. 4 WT4 3 WT3 2 WT2 1 WT1 0 WT0
Reset Value = 1000 0000b
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Table 59. Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS=1)
7 XTSCS Bit Number 6 Bit Mnemonic 5 SCICLK5 Description Smart Card Clock Selection Bit 7 XTSCS If XTSCS bit is set OR EXT48 bit is set (in PLLCON register) , CK_PLL is used to generate CK_ISO. Otherwise, CK_XTAL1 is used to generate CK_ISO. See the Clock Tree diagram figure 17. 6 Reserved The value read from this bit is indeterminate. Do not change these bits. SCIB clock reload register Prescaler 2 reload value is used to defines the card clock frequency. If SCICLK[5:0] is smaller than 48 : 5-0 SCICLK[5:0] Fck_iso = Fck_pll or Fck_XTAL1/ (2 * (48 - SCICLK[5:0])) If SCICLK[5:0] is equal to 48 : Fck_iso = Fck_XTAL1 SCICLK[5:0] must be smaller than 49. 4 SCICLK4 3 SCICLK3 2 SCICLK2 1 SCICLK1 0 SCICLK0
Reset Value = 0X10 1111b (default value for a divider by two)
DC/DC Converter
The Smart Card voltage (CVCC) is supplied by the integrated DC/DC converter which is controlled by several registers: * * * The SCICR register (Table 44 on page 79) controls the CVCC level by means of bits VCARD[1:0]. The SCCON register (Table 45 on page 80) enables to switch the DC/DC converter on or off by means of bit CARDVCC. The DCCKPS register (Table 61 on page 94) controls the DC/DC clock and current.
The DC/DC converter cannot be switched on while the CPRES pin remains inactive. If CPRES pin becomes inactive while the DC/DC converter is operating an automatic shut down sequence of the DC/DC converter is initiated by the electronics. It is mandatory to switch off the DC/DC Converter before entering in Power-down mode. Configuration The DC/DC Converter can work in two different modes which are selected by bit MODE in DCCKPS register: * * Pump Mode: an external inductance of 10 H must be connected between pins LI and VCC. VCC can be higher or lower than CVCC. Regulator mode : no external inductance is required but VCC must be always higher than CVCC+0.3V. The Regulation mode will work even if an external inductance of 10 H is connected between pins LI and VCC
The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS register must be configured to set the DC/DC clock to a working frequency of 4 MHz which depends upon the value of the crystal. There is no need to change the default configuration set by the reset sequence if an 8 MHz crystal is used by the application. The DC/DC Converter implements a current overflow controller which avoids permanent damage of the DC/DC converter in case of short circuit between CVCC and CVSS. The maximum limit is around 100 mA. It is possible to increase this limit in normal operating
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mode by 20% by means of bit OVFADJ in DCCKPS register. When the current overflow controller is operating, the ICARDOVF is set by the hardware in SCISR register. The current drawn from power supply by the DC/DC converter is controlled during the startup phase in order to avoid high transient current mainly in Pump Mode which could cause the power supply voltage to drop dramatically. This control is done by means of bits BOOST[1:0], which increases progressively the startup current level. Initialization Procedure The initialization procedure is different depending upon the required Card Vcc. One procedure apply for Card Vcc =< 3 volts and one procedure for Card Vcc = 5 volts. The initialization procedure involves : * * * * Procedure for CVcc =< 3 volts Select the CVCC level by means of bits VCARD[1:0] in SCICR register, Set bits BOOST[1:0] in DCCKPS register following the current level control wanted. Switch the DC/DC on by means of bit CARDVCC in SCCON register, Monitor bit VCARDOK in SCISR register in order to know when the DC/DC Converter is ready (CVCC voltage has reached the expected level)
The DC/DC regulation mode must be selected for Card Vcc = 1.8 volts and Card Vcc = 3 volts (MODE = 1 in DCCKPS register) The detailed procedures is described in flow chart of Figure 46. for Card Vcc = 1.8 volts and in the flow chart of Figure 47. for Card Vcc = 3 volts
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Figure 46. Card Vcc = 1.8V Initialization Procedure
SCICR.7=Reset=1
SCICR.7=Reset=0 VCARD[1:0] = 01
Mode Regulation DCCKPS[7]=1 BOOST[1:0]=01 SCCON CardVcc=1
Set Timeout to 3 ms
VCARDOK=1
Timeout Expired
DC/DC Initialization successful
DC/DC Initialization Failure
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Figure 47. Card Vcc = 3V Initialization Procedure
SCICR.7=Reset=1
SCICR.7=Reset=0 VCARD[1:0] = 10
Mode Regulation DCCKPS[7]=1 BOOST[1:0]=01 SCCON CardVcc=1
Set Timeout to 3 ms
VCARDOK=1
Timeout Expired
DC/DC Initialization successful
DC/DC Initialization Failure
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Procedure for CVcc = 5volts
The DC/DC pump mode must be selected (MODE = 0 in DCCKPS register). The detailed procedure is described in flow chart of Figure 48. VCC must be higher than 4.0 Volts.
Figure 48. Card Vcc = 5V Initialization Procedure
SCICR.7=Reset=1 SCICR.7=Reset=0 VCARD[1:0] = 11
Mode Pump DCCKPS[7]=0 BOOST[1:0]=[0:0] SCCON CardVcc=1
Set Timeout to 3 ms
VCARDOK=1
Timeout Expired
BOOST[1:0] = [0:0]
BOOST[1:0] = max = 3?
Decrement BOOST[1:0] to adjust the current overflow
Increment BOOST [1:0]
DC/DC Initialization Successful
DC/DC Initialization Failure
While VCC remains higher than 4.0V and startup current lower than 30 mA (depending on the load type), the DC/DC converter should be ready without having to increment BOOST[1:0] bits beyond [0:0] level. If VCC > 4.0V and startup current > 30 mA, it will be necessary to increment the BOOST[1:0] bits until the DC/DC converter is ready. 92
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Incrementation of BOOST[1:0] bits increases at the same time the current overflow level in the same proportion as the startup current. So once the DC/DC converter is ready it is advised to decrement the BOOST[1:0] bits to restore the overflow current to its normal or desired value.
Monitoring Procedure
Once the DC/DC has been successfuly initialized, it is necessary to monitor the DC/DC converter by means of bits VCARDOK and ICARDOVF in the SCISR register.
Table 60. DC/DC converter status
VCARDOK ICARDOVF DC/DC Status - Not Started or switched off by application. The current overflow sensor is disabled during the DC/DC converter startup. Then if a current overflow condition is applied during the DC/DC converter startup, the DC/DC converter is unable to start and both bits VCARDOK and ICARDOVF remains at 0. DC/DC converter correctly started then the output voltage is out of ISO/IEC 7816-3 specifications. In this case the firmware must take appropriate actions like deactivating the DC/DC converter in compliance with ISO/IEC 7816. 0 1 1 1 0 1 Started and automatically switched off by a current overflow condition Operating properly according to ISO/IEC 7816-3 and EMV recommendations Not applicable
0
0
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DC/DC Converter register Table 61. DC/DC Converter Control Register - DCCKPS (S:BFh)
7 MODE Bit Number 6 OVFADJ Bit Mnemonic 5 BOOST1 Description Regulation mode 7 MODE 0 : Pump mode (External Inductance required) 1 : Regulator mode (No External inductance required if VCC > CVCC+0.3V) Current Overflow Adjustment on Smart Card terminal 6 OVFADJ 0 : normal: 100 mA average 1 : normal + 20% VCARDOK=0 Maximum Startup Current drawn from power supply 5-4 BOOST[1:0] 00 : Normal: 30 mA average 01 : Normal + 30% 10 : Normal + 50% 11 : Normal + 80% DC/DC Clock Prescaler Value 0000 : Division factor: 2 (reset value) 0001 : Division factor: 3 0010 : Division factor: 4 0011 : Division factor: 5 3-0 DCCKPS[3:0] 0100 : Division factor: 6 0101 : Division factor: 8 0110 : Division factor: 10 0111 : Division factor: 12 1000 : Division factor: 24 Other values are reserved VCARDOK=1 Current Overflow Level on Smart Card terminal 00 : Normal = OVFADJ 01 : Normal + 30% 10 : Normal + 50% 11 : Normal + 80% 4 BOOST0 3 DCCKPS3 2 DCCKPS2 1 DCCKPS1 0 DCCKPS0
Reset Value = 0000 0000b
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USB Controller
The AT8xC5122D implements a USB device controller supporting Full Speed data transfer. In addition to the default control endpoint 0, it provides 6 other endpoints, which can be configured in Control, Bulk, Interrupt or Isochronous modes: * * * * Endpoint 0: 32-byte FIFO, default control endpoint Endpoint 1,2,3: 8-byte FIFO Endpoint 4,5: 64-byte FIFO Endpoint 6: 2 x 64-byte Ping-pong FIFO
This allows the firmware to be developed conforming to most USB device classes, for example: * * * * USB Mass Storage Classes USB Mass Storage Class CBI Transport Within the CBI framework, the Control endpoint is used to transport command blocks as well as to transport standard USB requests. One Bulk-Out endpoint is used to transport data from the host to the device. One Bulk-In endpoint is used to transport data from the device to the host. And one interrupt endpoint may also be used to signal command completion (protocol 0); it is optional and may not be used (protocol 1). The following configuration adheres to these requirements: * * * * USB Mass Storage Class BulkOnly Transport Endpoint 0: 8 bytes, Control In-Out Endpoint 4: 64 bytes, Bulk-Out Endpoint 5: 64 bytes, Bulk-In Endpoint 1: 8 bytes, Interrupt In USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.0 December 14, 1998. USB Mass Storage Class Bulk-Only Transport, Revision 1.0 - September 31, 1999. USB Human Interface Device Class, Version 1.1 - April 7, 1999. USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999.
Within the Bulk-Only framework, the Control endpoint is only used to transport classspecific and standard USB requests for device set-up and configuration. One Bulk-Out endpoint is used to transport commands and data from the host to the device. One BulkIn endpoint is used to transport status and data from the device to the host. No interrupt endpoint is needed. The following configuration adheres to these requirements: * * * Endpoint 0: 8 bytes, Control In-Out Endpoint 4: 64 bytes, Bulk-Out Endpoint 5: 64 bytes, Bulk-In
USB Device Firmware Upgrade (DFU)
The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip program memory of the AT8xC5122D. This allows the implementation of product enhancements and patches to devices that are already in the field. Two different configurations and description sets are used to support DFU functions. The Run-Time configuration co-exists with the usual functions of the device, which may be USB Mass Storage for the AT8xC5122D. It is used to initiate DFU from the normal operating mode. The DFU configuration is used to perform the firmware update after device re-configuration and USB reset. It excludes any other function. Only the default control pipe (endpoint 0) is used to support DFU services in both configurations.
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The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes, which is the size of the FIFO implemented for endpoint 0.
Description
The USB device controller provides the hardware that the AT8xC5122D and the AT83C5123 need to interface a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48 MHz reference clock, which is the output of the AT8xC5122D/23 PLL (see Section "Phase Lock Loop (PLL)", page 42) divided by a clock prescaler. This clock is used to generate a 12 MHz full speed bit clock from the received USB differential data and to transmit data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus. The Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC generation and checking, and the serial-parallel data conversion. The Universal Function Interface (UFI) performs the interface between the data flow and the Dual Port Ram Figure 49. USB Device Controller Block Diagram 48 MHz +/- 0.25%
DPLL
12MHz C51 Microcontroller Interface
D+ D-
USB D+/DBuffer
UFI
Up to 48 MHz UC_SYSCLK
SIE
Serial Interface Engine (SIE)
The SIE performs the following functions: * * * * * * * NRZI data encoding and decoding. Bit stuffing and unstuffing. CRC generation and checking. Handshakes. TOKEN type identifying. Address checking. Clock generation (via DPLL).
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Figure 50. SIE Block Diagram
End of Packet Detection Start of Packet Detection SYNC detection
D+ D-
NRZI ` NRZ Bit Unstuffing Packet bit counter
PID decoder
Clock Recovery Clk48 (48 MHz)
SysClk (12 MHz)
DataOut Address Decoder Serial to Parallel 8 Conversion
USB Pattern Generator Parallel to Serial Converter Bit Stuffing NRZI Converter CRC16 Generator
CRC5 & CRC16 Generation/Check
8
DataIn [7:0]
Function Interface Unit (UFI)
The Function Interface Unit provides the interface between the AT8xC5122D (or AT83C5123) and the SIE. It manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. Figure 51. UFI Block Diagram
UFI DPLL
Transfer Control FSM Asynchronous Information Transfer Endpoint 6 Endpoint 5 Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 User DPRAM CSREG 0 to 7 C51 Microcontroller Interface
Registers Bank
SIE
DPR Control USB side
DPR Control mP side
Up to 48 MHz UC_SYSCLK
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Figure 52. Minimum Intervention from the USB Device Firmware
OUT Transactions:
HOST UFI C51
OUT DATA0 (n Bytes) ACK
OUT interrupt C51
DATA1 NACK
OUT
DATA1 ACK
Endpoint FIFO read (n bytes)
IN Transactions:
HOST UFI C51
IN NACK Endpoint FIFO write
IN DATA1
IN DATA1
ACK interrupt C51 Endpoint FIFO write
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Configuration
General Configuration * USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (Section "Clock Controller", page 41). The USB controller should be then enabled by setting the USBE bit in the USBCON register. * Set address After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the USBADDR register. This action will allow the USB controller to answer to the requests sent at the address 0. When a SET_ADDRESS request has been received, the USB controller must only answer to the address defined by the request. The new address should be stored in the USBADDR register. The FEN bit and the FADDEN bit in the USBCON register should be set to allow the USB controller to answer only to requests sent at the new address. * Set configuration The CONFG bit in the USBCON register should be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should be cleared. Endpoint Configuration * Selection of an Endpoint
The endpoint register access is performed using the UEPNUM register. The following registers correspond to the endpoint whose number is stored in the UEPNUM register. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM register. - - - - UEPSTAX, UEPCONX, UEPDATX, UBYCTX,
Figure 53. Endpoint Selection
Endpoint 0
UEPSTA0
UEPCON0 UBYCT0
UEPDAT0
0 1 2 3 4 5 6
SFR Registers X
UEPSTAX UEPCONX UBYCTX UEPDATX
Endpoint 6
UEPSTA6
UEPCON6 UBYCT6
UEPDAT6
UEPNUM
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*
Endpoint enable
Before using an endpoint, this one should be enabled by setting the EPEN bit in the UEPCONX register. An endpoint which is not enabled won't answer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests. * Endpoint type configuration
All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The configuration of an endpoint is performed by setting the field EPTYPE with the following values: - - - - Control: Isochronous: Bulk: Interrupt: EPTYPE = 00b EPTYPE = 01b EPTYPE = 10b EPTYPE = 11b
The Endpoint 0 is the Default Control Endpoint and should always be configured in Control type. * Endpoint direction configuration
For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the following values: - - IN:EPDIR = 1b OUT:EPDIR = 0b
For Control endpoints, the EPDIR bit has no effect. * Summary of Endpoint Configuration:
Make sure to select the correct endpoint number in the UEPNUM register before accessing to endpoint specific registers. Table 62. Summary of Endpoint Configuration
Endpoint configuration Disabled Control Bulk-In Bulk-Out Interrupt-In Interrupt-Out Isochronous-In Isochronous-Out EPEN 0b 1b 1b 1b 1b 1b 1b 1b EPDIR Xb Xb 1b 0b 1b 0b 1b 0b EPTYPE XXb 00b 10b 10b 11b 11b 01b 01b UEPCONX 0XXX XXXb 80h 86h 82h 87h 83h 85h 81h
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* Endpoint FIFO reset
Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its original value, resets the byte counter of the endpoint (UBYCTX register), and resets the data toggle bit (DTGL bit in UEPCONX). The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register. For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000 0000b in the UEPRST register.
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Read/Write Data FIFO
Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into the FIFO and the byte counter of the endpoint is updated (UBYCTX register). The firmware has to store the endpoint byte counter before any access to the endpoint FIFO. The byte counter is not updated when reading the FIFO. To read data from an endpoint, select the correct endpoint number in UEPNUM and read the UEPDATX register. This action automatically decreases the corresponding address vector, and the next data is then available in the UEPDATX register. Write Data FIFO The write access for each IN endpoint is performed using the UEPDATX register. To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and write into the UEPDATX register. The corresponding address vector is automatically increased, and another write can be carried out. Warning 1: The byte counter is not updated. Warning 2: Do not write more bytes than supported by the corresponding endpoint.
Figure 54. Endpoint FIFO Configuration 138H Endpoint 6 - bank 1 F8H Endpoint 6 - bank 0 B8H Endpoint 5 - bank 0 78H Endpoint 4 - bank 0 38H 30H 28H 20H 00H Endpoint 3 - bank 0 Endpoint 2 - bank 0 Endpoint 1 - bank 0 Endpoint 0 - bank 0 64 Bytes 64 Bytes 8 Bytes 8 Bytes 8 Bytes 32 Bytes 2 x 64 Bytes
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Base Addresses
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Bulk / Interrupt Transactions
Bulk/Interrupt OUT Transactions in Standard Mode Bulk and Interrupt transactions are managed in the same way.
Figure 55. Bulk/Interrupt OUT transactions in Standard Mode
HOST
OUT DATA0 (n bytes)
UFI
ACK RXOUTB0
C51
Endpoint FIFO read byte 1 OUT DATA1 NAK OUT DATA1 NAK OUT DATA1 ACK RXOUTB0 Endpoint FIFO read byte 1 Endpoint FIFO read byte n Clear RXOUTB0 Endpoint FIFO read byte 2
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct and the endpoint byte counter contains the number of bytes sent by the Host.
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Bulk/Interrupt OUT Transactions in Ping-Pong Mode (Endpoints 6)
Figure 56. Bulk / Interrupt OUT Transactions in Ping-Pong Mode
HOST
OUT DATA0 (n bytes)
UFI
ACK RXOUTB0
C51
Endpoint FIFO bank 0 - read byte 1 OUT DATA1 (m bytes) ACK Endpoint FIFO bank 0 - read byte 2 Endpoint FIFO bank 0 - read byte n Clear RXOUTB0 OUT DATA0 (p bytes) ACK RXOUTB1 Endpoint FIFO bank 1 - read byte 1 Endpoint FIFO bank 1 - read byte 2 Endpoint FIFO bank 1 - read byte m RXOUTB0 Clear RXOUTB1 Endpoint FIFO bank 0 - read byte 1 Endpoint FIFO bank 0 - read byte 2 Endpoint FIFO bank 0 - read byte p Clear RXOUTB0
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint FIFO. When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1 endpoint FIFO. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new valid packet receipt. The firmware has to clear one of these two bits after having read all the data FIFO to allow a new valid packet to be stored in the corresponding bank. A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware.
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If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Bulk/Interrupt IN Transactions In Standard Mode Figure 57. Bulk/Interrupt IN Transactions in Standard Mode
HOST
IN NAK
UFI
C51
Endpoint FIFO write byte 1 Endpoint FIFO write byte 2 Endpoint FIFO write byte n Set TXRDY
IN DATA0 (n bytes) ACK TXCMPL Clear TXCMPL Endpoint FIFO write byte 1
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. To send a Zero Length Packet, the firmware should set the TXRDY bit without writing any data into the endpoint FIFO. Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK handshake for each IN requests. To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored in the endpoint FIFO is then cleared and a new packet can be written and sent. When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller.
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Bulk/Interrupt IN Transactions in Ping-Pong Mode
Figure 58. Bulk / Interrupt IN transactions in Ping-Pong mode
HOST
IN
UFI
C51
Endpoint FIFO Bank 0 - Write Byte 1 Endpoint FIFO Bank 0 - Write Byte 2
NACK Endpoint FIFO Bank 0 - Write Byte n Set TXRDY IN DATA0 (n Bytes) ACK Endpoint FIFO Bank 1 - Write Byte m TXCMPL Clear TXCMPL Set TXRDY DATA1 (m Bytes) ACK Endpoint FIFO Bank 0 - Write Byte 1 Endpoint FIFO Bank 0 - Write Byte 2 Endpoint FIFO Bank 0 - Write Byte p TXCMPL IN DATA0 (p Bytes) ACK Clear TXCMPL Set TXRDY Endpoint FIFO Bank 1 - Write Byte 1 Endpoint FIFO Bank 1 - Write Byte 1 Endpoint FIFO Bank 1 - Write Byte 2
IN
An endpoint will be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller will answer a NAK handshake for each IN requests concerning this bank. Note that in the example above, the firmware clears the Transmit Complete bit (TXCMPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1. The firmware will never write more bytes than supported by the endpoint FIFO.
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Control Transactions
Setup Stage The DIR bit in the UEPSTAX register should be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the Rxsetup bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an interrupt is triggered if enabled. The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing the RXSETUP bit to free the endpoint FIFO for the next transaction. The data stage management is similar to Bulk management. A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX register. * If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has been set by the hardware. The firmware should clear the TXCMPL bit before any other transaction. If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new valid packet has been received on the endpoint. The firmware must read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction.
Data Stage: Control Endpoint Direction
*
The bit DIR is used to send the correct data toggle in the data stage. To send a STALL handshake, see "STALL Handshake" on page 110. Status Stage The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage. The status stage management is similar to Bulk management. * For a Control Write transaction or a No-Data Control transaction, the status stage consists of a IN Zero Length Packet (see "Bulk/Interrupt IN Transactions In Standard Mode" on page 105). To send a STALL handshake, see "STALL Handshake" on page 110. For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see "Bulk/Interrupt OUT Transactions in Standard Mode" on page 103).
*
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Isochronous Transactions
Isochronous OUT Transactions in Standard Mode An endpoint should be first enabled and configured before being able to receive Isochronous packets. When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost. If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only the remaining bytes into the FIFO. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous OUT Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to receive Isochronous packets. When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO will be lost. If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB controller will store only the remaining bytes into the FIFO. When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be lost. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new packet receipt. The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank.
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If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous IN Transactions in Standard Mode An endpoint should be first enabled and configured before being able to send Isochronous packets. The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more bytes than supported by the endpoint FIFO. Isochronous IN Transactions in Ping-Pong Mode An endpoint should be first enabled and configured before being able to send Isochronous packets. The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller won't send anything at each IN requests concerning this bank. The firmware should never write more bytes than supported by the endpoint FIFO.
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Miscellaneous
USB Reset The EORINT bit in the USBINT register is set by hardware when a End of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still enabled, but all the USB registers are reset by hardware. The firmware should clear the EORINT bit to allow the next USB reset detection. This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an interrupt if enabled. The firmware should clear the STALLRQ and STLCRC bits after each STALL sent. The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on a CONTROL type endpoint. Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the next Start of Frame detection. When receiving a Start of Frame, the frame number is automatically stored in the UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of Frame is valid (CRCOK set at 1) or corrupt (CRCERR set at 1). The UFNUML and UFNUMH registers are automatically updated when receiving a new Start of Frame. The Data Toggle bit is set by hardware when a DATA 0 packet is received and accepted by the USB controller and cleared by hardware when a DATA 1 packet is received and accepted by the USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST register. For Control endpoints, each SETUP transaction starts with a DATA 0 and data toggling is then used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a DATA 1 (for a control read transfer). For Isochronous endpoints, the device firmware should ignore the data-toggle. NAK Handshakes When a NAK handshake is sent by the USB controller to a IN or OUT request from the Host, the NAKIN or NAKOUT bit is set by hardware. This information can be used to determine the direction of the communication during a Control transfer. These bits are cleared by software.
STALL Handshake
Frame Number
Data Toggle Bit
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Suspend/Resume Management
Suspend The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active. The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-up event is detected. The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit in the USBCON register. 2. Disable the PLL by clearing the PLLEN bit in the PLLCON register. Resume When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated.
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Figure 59. Example of a Suspend/Resume Management
USB Controller Init SPINT Detection of a SUSPEND State Clear SPINT Set SUSPCLK Disable PLL
microcontroller in power-down
Put the USB pads in power down mode
Detection of a RESUME State Note : WUPCPU bit must be Cleared before enabling the PLL
WUPCPU
Clear SUSPCLK Clear WUPCPU bit Enable PLL
Upstream Resume
A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose. When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RMWUPE bit in the USBCON register to enable this function. RMWUPE value should be 0 in the other cases. If the device is in SUSPEND mode, the USB controller can send an upstream resume by clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the USBCON register. The USB controller sets to 1 the UPRSM bit in the USBCON register. All clocks must be enabled first. The Remote Wake is sent only if the USB bus was in Suspend state for at least 5 ms. When the upstream resume is completed, the UPRSM bit is reset to 0 by hardware. The firmware should then clear the SDRMWUP bit.
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Figure 60. Example of REMOTE WAKEUP Management
USB Controller Init
SET_FEATURE: DEVICE_REMOTE_WAKEUP Set RMWUPE SPINT Detection of a SUSPEND state Suspend management Need USB Resume
Enable Clocks Clear SPINT UPRSM = 1 UPRSM Clear SDRMWUP Set SDMWUP
upstream RESUME sent
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Detach Simulation
In order to be re-enumerated by the Host, the AT8xC5122/23 has the possibility to simulate a DETACH-ATTACH of the USB bus. The VREF output voltage is between 3.0V and 3.6V. This output can be connected to the D+ pull-up as shown in Figure 61. This output can be put in high-impedance when the DETACH bit is set to 1 in the USBCON register. Maintaining this output in high impedance for more than 3 s will simulate the disconnection of the device. When resetting the DETACH bit, an ATTACH is then simulated. The USB controller should be enabled to use this feature. Figure 61. Example of VREF Connection VREF
R1 DD+ R2
1 2 3 4 VCC DD+ GND USB-B Connector
R3
Figure 62. Disconnect Timing D+ VIHZ(min)
VIL VSS D>= 2,5 s
Device Disconnected
Disconnect Detected
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USB Interrupt System
Interrupt System Priorities Figure 63. USB Interrupt Control System
D+ D-
USB Controller EUSB
IEN1.6
00 01 10 11
EA
IEN0.7
Interrupt Enable
IPH/L Priority Enable
Lowest Priority Interrupts
Table 63. Priority Levels
IPHUSB 0 0 1 1 IPLUSB 0 1 0 1 USB Priority Level 0 Lowest 1 2 3 Highest
Interrupt Control System
As shown in Figure 64, many events can produce a USB interrupt: * * * TXCMPL: Transmitted In Data (Table 70 on page 121). This bit is set by hardware when the Host accept a In packet. RXOUTB0: Received Out Data Bank 0 (Table 70 on page 121). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0. RXOUTB1: Received Out Data Bank 1 (only for Ping-Pong endpoints) (Table 70 on page 121). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 1. RXSETUP: Received Setup (Table 70 on page 121). This bit is set by hardware when an SETUP packet is accepted by the endpoint. NAKIN and NAKOUT: These bits are set by hardware when a Nak Handshake has been received on the corresponding endpoint. These bits are cleared by software. STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table on page 122). This bit is set by hardware when a STALL handshake has been sent as requested by STALLRQ, and is reset by hardware when a SETUP packet is received. SOFINT: Start Of Frame Interrupt (Table 65 on page 118). This bit is set by hardware when a USB start of frame packet has been received. WUPCPU: Wake-Up CPU Interrupt (Table 65 on page 118). This bit is set by hardware when a USB resume is detected on the USB bus, after a SUSPEND state. SPINT: Suspend Interrupt (Table 65 on page 118). This bit is set by hardware when a USB suspend is detected on the USB bus.
* * *
* * *
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Figure 64. USB Interrupt Control Block Diagram Endpoint X (X = 0..6)
TXCMP
UEPSTAX.0
RXOUTB0
UEPSTAX.1
RXOUTB1
UEPSTAX.6
EPXINT
UEPINT.X
RXSETUP
UEPSTAX.2
EPXIE
UEPIEN.X
STLCRC
UEPSTAX.3
NAKOUT
UEPCONX.5
NAKIN
UEPCONX.4
NAKIEN
UEPCONX.6
WUPCPU
USBINT.5
EUSB
EWUPCPU
USBIEN.5 IE1.6
EORINT
USBINT.4
EEORINT
USBIEN.4
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0
ESPINT
USBIEN.0
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Registers
Table 64. USB Global Control Register - USBCON (S:BCh)
7 USBE Bit Number 6 SUSPCLK Bit Mnemonic 5 SDRMWUP 4 DETACH 3 UPRSM 2 RMWUPE 1 CONFG 0 FADDEN
Description USB Enable Set this bit to enable the USB controller. Clear this bit to disable and reset the USB controller, to disable the USB transceiver and to disable the USB controller clock inputs. Suspend USB Clock Set this bit to disable the 48MHz clock input (Resume Detection is still active). Clear this bit to enable the 48MHz clock input.
7
USBE
6
SUSPCLK
5
Send Remote Wake-up Set this bit to force an external interrupt on the USB controller for Remote Wake UP purpose. SDRMWUP An upstream resume is send only if the bit RMWUPE is set, all USB clocks are enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM below. This bit is cleared by software. Detach Command Set this bit to simulate a Detach on the USB line. The VREF pin is then in a floating state. Clear this bit to maintain VREF at 3.3V. Upstream Resume (read only) This bit is set by hardware when SDRMWUP has been set and if RMWUPE is enabled. This bit is cleared by hardware after the upstream resume has been sent. Remote Wake-Up Enable Set this bit to enabled request an upstream resume signaling to the host. Clear this bit otherwise. Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP feature for the device. Configured This bit should be set by the device firmware after a SET_CONFIGURATION request with a non-zero value has been correctly processed. It should be cleared by the device firmware when a SET_CONFIGURATION request with a zero value is received. It is cleared by hardware on hardware reset or when an USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times: typically 2.7 s). Function Address Enable This bit should be set by the device firmware after a successful status phase of a SET_ADDRESS transaction. It should not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset or when an USB reset is received (see above). When this bit is cleared, the default function address is used (0).
4
DETACH
3
UPRSM
2
RMWUPE
1
CONFG
0
FADDEN
Reset Value = 0000 0000b
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Table 65. USB Global Interrupt Register - USBINT (S:BDh)
7 6 5 WUPCPU 4 EORINT 3 SOFINT 2 1 0 SPINT
Bit Bit Number Mnemonic Description 7-6 Reserved The value read from these bits is always 0. Do not change these bits.
5
Wake-up CPU Interrupt This bit is set by hardware when the USB controller is in SUSPEND state and is re-activated by a non-idle signal FROM USB line (not by an upstream resume). WUPCPU This triggers a USB interrupt when EWUPCPU is set in the Table on page 119. When receiving this interrupt, user has to enable all USB clock inputs. This bit should be cleared by software (USB clocks must be enabled before). End of Reset Interrupt This bit is set by hardware when a End of Reset has been detected by the USB EEORINT controller. This triggers a USB interrupt when EEORINT is set in the Table on page 119. This bit should be cleared by software. Start Of Frame Interrupt This bit is set by hardware when an USB Start Of Frame PID (SOF) has been detected. This triggers a USB interrupt when ESOFINT is set in the Table on page 119. This bit should be cleared by software. Reserved The value read from these bits is always 0. Do not change these bits. Suspend Interrupt This bit is set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN register (Table 66 on page 119). This bit must be cleared by software before powering the microcontroller down as it disables the USB pads to reduce the power consumption.
4
3
SOFINT
2-1
-
0
SPINT
Reset Value = 0000 0000b
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Table 66. USB Global Interrupt Enable Register - USBIEN (S:BEh)
7
-
6
-
5
EWUPCPU
4
EEORINT
3
ESOFINT
2
-
1
-
0
ESPINT
Bit Number 7-6
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not change these bits.
5
Enable Wake-up CPU Interrupt EWUPCPU Set this bit to enable Wake-up CPU Interrupt. Clear this bit to disable Wake-up CPU Interrupt. EEORINT Enable End of Reset Interrupt Set this bit to enable End of Reset Interrupt. This bit is set after reset. Clear this bit to disable End of Reset Interrupt. Enable SOF Interrupt Set this bit to enable SOF Interrupt. Clear this bit to disable SOF Interrupt. Reserved The value read from these bits is always 0. Do not change these bits. Enable Suspend Interrupt Set this bit to enable Suspend Interrupts (See Table 65 on page 118). Clear this bit to disable Suspend Interrupts.
4
3
ESOFINT
2-1
-
0
ESPINT
Reset Value = 0001 0000b Table 67. USB Address Register - USBADDR (S:C6h)
7 FEN Bit Number 7 6 UADD6 Bit Mnemonic FEN 5 UADD5 4 UADD4 3 UADD3 2 UADD2 1 UADD1 0 UADD0
Description Function Enable Set this bit to enable the function. FADD is reset to 1. Cleared this bit to disable the function.
6-0
USB Address This field contains the default address (0) after power-up or USB bus reset. UADD[6:0] It should be written with the value set by a SET_ADDRESS request received by the device firmware.
Reset Value = 1000 0000b
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Table 68. USB Endpoint Number - UEPNUM (S:C7h)
7 Bit Number 7-4 6 Bit Mnemonic 5 Description Reserved The value read from these bits is always 0. Do not change these bits. Endpoint Number Set this field with the number of the endpoint which should be accessed when reading or writing to, USB Byte Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX (S:E2h) or USB Endpoint X Control Register UEPCONX (S:D4h). This value can be 0, 1, 2, 3, 4, 5 or 6. 4 3 EPNUM3 2 EPNUM2 1 EPNUM1 0 EPNUM0
3-0
EPNUM[3:0]
Reset Value = 0000 0000b
Table 69. USB Endpoint X Control Register - UEPCONX (S:D4h)
7 EPEN Bit Number 6 NAKIEN Bit Mnemonic 5 NAKOUT Description Endpoint Enable Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will always be enabled after a hardware or USB bus reset and participate in the device configuration. Clear this bit to disable the endpoint according to the device configuration. NAK Interrupt Enable Set this bit to enable NAKIN and NAKOUT Interrupt. Clear this bit to disable NAKIN and NAKOUT Interrupt. NAK OUT Sent This bit is set by hardware when the a NAK handshake is sent by the USB controller to an OUT request from the Host. This generates an interrupt if the NAKIEN bit is set. This bit shall be cleared by software. NAK IN Sent This bit is set by hardware when the a NAK handshake is sent by the USB controller to an IN request from the Host. This generates an interrupt if the NAKIEN bit is set. This bit shall be cleared by software. Data Toggle (Read-only) This bit is set by hardware when a valid DATA0 packet is received and accepted. This bit is cleared by hardware when a valid DATA1 packet is received and accepted. Endpoint Direction Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. This bit has no effect for Control endpoints. Endpoint Type Set this field according to the endpoint configuration (Endpoint 0 will always be configured as control): 00Control endpoint 01Isochronous endpoint 10Bulk endpoint 11Interrupt endpoint 4 NAKIN 3 DTGL 2 EPDIR 1 EPTYPE1 0 EPTYPE0
7
EPEN
6
NAKIEN
5
NAKOUT
4
NAKIN
3
DTGL
2
EPDIR
1-0
EPTYPE[1:0]
Reset Value = 1000 0000b when UEPNUM = 0 Reset Value = 0000 0000b otherwise
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Table 70. USB Endpoint Status and Control Register X - UEPSTAX (S:CEh) X=EPNUM set in UEPNUM Register)
7 DIR 6 RXOUTB1 5 STALLRQ 4 TXRDY 3 STL/CRC 2 RXSETUP 1 RXOUTB0 0 TXCMP
Bit Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (see"USB Endpoint X Control Register - UEPCONX (S:D4h)" on page 120). This bit determines the Control data and status direction. The device firmware should set this bit ONLY for the IN data stage, before any other USB operation. Otherwise, the device firmware should clear this bit.
7
DIR
6
Received OUT Data Bank 1 for Endpoint 6 (Ping-pong Mode) This bit is set by hardware after a new packet has been stored in the endpoint FIFO Data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is triggered if enabled (see "USB Global Interrupt Register - USBINT (S:BDh)" on page 118) and all RXOUTB1 the following OUT packets to the endpoint bank 1 are rejected (NAK'ed) until this bit has been cleared, excepted for Isochronous Endpoints. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO. Stall Handshake Request Set this bit to request a STALL answer to the host for the next handshake. STALLRQ Clear this bit otherwise. For CONTROL endpoints: cleared by hardware when a valid SETUP PID is received. TX Packet Ready Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is triggered if enabled (see Table 65 on page 118). Stall Sent / CRC error flag - For Control, Bulk and Interrupt Endpoints: This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint interrupt is triggered if enabled (see"" on page 118) It should be cleared by the device firmware. - For Isochronous Endpoints (Read-Only): This bit is set by hardware if the last received data is corrupted (CRC error on data). This bit is updated by hardware when a new data is received.
5
4
TXRDY
3
STLCRC
2
Received SETUP This bit is set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the register RXSETUP are cleared by hardware and the endpoint interrupt is triggered if enabled (see Table 65 on page 118). It should be cleared by the device firmware after reading the SETUP data from the endpoint FIFO. Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints) This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint interrupt is triggered if enabled (see"" on page 118) and all the following OUT packets to the endpoint bank 0 are rejected (NAK'ed) until this RXOUTB0 bit has been cleared, excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the content of the endpoint FIFO, even if its Data packet is received while this bit is set. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO. Transmitted IN Data Complete This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been accepted (ACK'ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled (see Table 65). This bit should be cleared by the device firmware before setting TXRDY.
1
0
TXCMPL
Reset Value = 0000 0000b
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Table 71. USB FIFO Data Endpoint X (X=EPNUM set in UEPNUM Register) UEPDATX (S:CFh)
7 FDAT7 Bit Number 7-0 6 FDAT6 Bit Mnemonic 5 FDAT5 4 FDAT4 3 FDAT3 2 FDAT2 1 FDAT1 0 FDAT0
Description Endpoint X FIFO data
FDAT[7:0] Data byte to be written to FIFO or data byte to be read from the FIFO, for the
Endpoint X (see EPNUM).
Reset Value = XXXX XXXXb Table 72. USB Byte Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX (S:E2h)
7 Bit Number 7 6 BYCT6 5 BYCT5 4 BYCT4 3 BYCT3 2 BYCT2 1 BYCT1 0 BYCT0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not change this bit.
6-0
Byte Count LSB BYCT[6:0] Least Significant Byte of the byte count of a received data packet. This byte count is equal to the number of data bytes received after the Data PID.
Reset Value = 0000 0000b
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Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h)
7 Bit Number 7 6 EP6RST 5 EP5RST 4 EP4RST 3 EP3RST 2 EP2RST 1 EP1RST 0 EP0RST
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not change this bit. Endpoint 6 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Endpoint 5 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Endpoint 4 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Endpoint 3 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Endpoint 2 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Endpoint 1 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Endpoint 0 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO.
6
EP6RST
5
EP5RST
4
EP4RST
3
EP3RST
2
EP2RST
1
EP1RST
0
EP0RST
Reset Value = 0000 0000b
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Table 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only)
7 Bit Number 7 6 EP6INT 5 EP5INT 4 EP4INT 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not change this bit. Endpoint 6 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 6. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP6INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. Endpoint 5 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 5. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP5INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. Endpoint 4 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 4. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP4INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. Endpoint 3 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 3. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP3INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. Endpoint 2 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 2. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP2INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. Endpoint 1 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 1. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP1INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. Endpoint 0 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 0. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP0INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared.
6
EP6INT
5
EP5INT
4
EP4INT
3
EP3INT
2
EP2INT
1
EP1INT
0
EP0INT
Reset Value = 0000 0000b
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Table 75. USB Endpoint Interrupt Enable Register - UEPIEN (S:C2h)
7 Bit Number 7 6 EP6INTE 5 EP5INTE 4 EP4INTE 3 EP3INTE 2 EP2INTE 1 EP1INTE 0 EP0INTE
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not change this bit. Endpoint 6 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 5 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 4 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 3 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 2 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 1 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 0 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint.
6
EP6INTE
5
EP5INTE
4
EP4INTE
3
EP3INTE
2
EP2INTE
1
EP1INTE
0
EP0INTE
Reset Value = 0000 0000b
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Serial I/O Port
The serial I/O port in the AT8xC5122/23 is compatible with the serial I/O port in the 80C52. The I/O port provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three fullduplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: * * Framing error detection Automatic address recognition
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (Modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 65). Figure 65. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h)
Set FE Bit if Stop Bit is 0 (Framing Error) (SMOD0 = 1) SM0 to UART Mode Control (SMOD0 = 0) SMOD1 SMOD0 POF GF1 GF0 PD IDL PCON (87h)
To UART Framing Error Control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Figure 70 on page 130) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 66 and Figure 67). Figure 66. UART Timings in Mode 1
RXD Start Bit RI SMOD0=X FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Data Byte
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Figure 67. UART Timings in Modes 2 and 3
RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 D8 Ninth Stop bit bit Data byte
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don't care bits (defined by zeros) to form the device's given address. The don't care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b
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The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't care bits, e.g.:
SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb
The use of don't care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b
For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don't care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that does not support automatic address recognition. When using the Timer 1, the Baud Rate is derived from the overflow of the timer. As shown in Figure 68 the Timer 1 is used in its 8-bit auto-reload mode). SMOD1 bit in PCON register allows doubling of the generated baud rate.
Timer 1
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Figure 68. Timer 1 Baud Rate Generator Block Diagram
CK_ T1
/6
0 1
TL1 (8 bits)
Overflow
/2
0 1
T1
To serial Port
C/T1#
TMOD.6
INT1# GATE1
TMOD.7
SMOD1
PCON.7
T1 CLOCK
TR1
TCON.6
TH1 (8 bits)
Internal Baud Rate Generator
When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 69 the Internal Baud Rate Generator is an 8-bit auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in BDRCON register (see Table 82 on page 136). The Internal Baud Rate Generator is enabled by setting BRR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated baud rate. Figure 69. Internal Baud Rate Generator Block Diagram
CK_ SI
/6
0 1
BRG (8 bits) BRR
BDRCON.4
Overflow
/2
0 1
To serial Port
SPD
BDRCON.1
SMOD1
PCON.7
IBRG CLOCK
BRL (8 bits)
Synchronous Mode (Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data. The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)"). Figure 70 shows the serial port block diagram in Mode 0.
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Figure 70. Serial I/O Port Block Diagram (Mode 0)
SCON.6 SM1 SCON.7 SM0 SBUF Tx SR RXD
Mode Decoder M3 M2 M1 M0
SBUF Rx SR Mode Controller CK_ T1 TI SCON.1 RI SCON.0 IBRG CLOCK Baud Rate Controller
TXD
Transmission (Mode 0)
To start a transmission mode 0, write to SCON register clearing bits SM0, SM1. As shown in Figure 71, writing the byte to transmit to SBUF register starts the transmission. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle composed of a high level then low level signal on TXD. During the eighth clock cycle the MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to indicate the end of the transmission. Figure 71. Transmission Waveforms (Mode 0)
TXD Write to SBUF RXD TI
D0 D1 D2 D3 D4 D5 D6 D7
Reception (Mode 0)
To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting the REN bit. As shown in Figure 72, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0 bit is then shifted into the shift register. After eight sampling, the MSB (D7) is shifted into the shift register, and hardware asserts RI bit to indicate a completed reception. Software can then read the received byte from SBUF register. Figure 72. Reception Waveforms (Mode 0)
TXD Write to SCON RXD RI
Set REN, Clear RI D0 D1 D2 D3 D4 D5 D6 D7
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Baud Rate Selection (Mode 0) In mode 0, baud rate can be either fixed or variable. As shown in Figure 73, the selection is done using M0SRC bit in BDRCON register. Figure 74 gives the baud rate calculation formulas for each baud rate source. Figure 73. Baud Rate Source Selection (Mode 0)
CK_ SI IBRG CLOCK
/6
0 1
To Serial Port
M0SRC
BDRCON.0
Figure 74. Baud Rate Formulas (Mode 0)
Baud_Rate = Baud_Rate =
FCK_SI
2SMOD1 FCK_SI 6(1-SPD) 32 (256 -BRL) 2SMOD1 FCK_SI 32 Baud_Rate
6
BRL = 256 -
6
(1-SPD)
a. Fixed Formula
b. Variable Formula
Asynchronous Modes (Modes 1, 2 and 3)
The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 75 shows the Serial Port block diagram in such asynchronous modes. Figure 75. Serial I/O Port Block Diagram (Modes 1, 2 and 3)
SCON.6 SCON.7 SCON.3
SM1
SM0
TB8 SBUF Tx SR TXD
Mode Decoder
M3 M2 M1 M0 T1 CLOCK IBRG CLOCK CK_ SI
Rx SR Mode & Clock Controller SBUF Rx SM2
SCON.4
RXD
RB8
SCON.2
TI
SCON.1
RI
SCON.0
Mode 1
Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 76) consists of 10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. When a data is received, the stop bit is read in the RB8 bit in SCON register.
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Figure 76. Data Frame Format (Mode 1)
Mode 1
Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
8-bit data
Modes 2 and 3
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 77) consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alternatively, you can use the ninth bit as a command/data flag. Figure 77. Data Frame Format (Modes 2 and 3)
Modes 2 and 3
Start bit D0 D1 D2 D3 D4 9-bit data D5 D6 D7 D8 Stop bit
Transmission (Modes 1, 2 and 3) Reception (Modes 1, 2 and 3) Framing Error Detection (Modes 1, 2 and 3)
To initiate a transmission, write to SCON register, setting SM0 and SM1 bits according to Figure 70 on page 130, and setting the ninth bit by writing to TB8 bit. Then, writing the byte to be transmitted to SBUF register starts the transmission. To prepare for a reception, write to SCON register, setting SM0 and SM1 bits according to Figure 70 on page 130, and setting REN bit. The actual reception is then initiated by a detected high-to-low transition on the RXD pin. Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register as shown in Figure 78. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two devices. If a valid stop bit is not found, the software sets FE bit in SCON register. Software may examine FE bit after each reception to check for data errors. Once set, only software or a chip reset clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on stop bit instead of the last data bit as detailed in Figure 76 and Figure 77. Figure 78. Framing Error Block Diagram
Framing Error Controller
FE
1 0
SM0/FE
SCON.7
SM0 SMOD0
PCON.6
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Baud Rate Selection (Modes 1 and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate Generator and allows different baud rate in reception and transmission. As shown in Figure 79 the selection is done using RBCK and TBCK bits in BDRCON register. Figure 80 gives the baud rate calculation formulas for each baud rate source while Table 76 details Internal Baud Rate Generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. Figure 79. Baud Rate Source Selection (Modes 1 and 3)
T1 CLOCK IBRG CLOCK
0 1
/ 16
To serial reception Port
T1 CLOCK IBRG CLOCK
0 1
/ 16
To serial transmission Port
RBCK
BDRCON.2
TBCK
BDRCON.3
Figure 80. Baud Rate Formulas (Modes 1 and 3)
Baud_Rate = 6
(1-SPD)
2SMOD1 FCK_SI 32 (256 -BRL)
Baud_Rate =
2SMOD1 FCK_T1 6 32 (256 -TH1) 2SMOD1 FCK_T1 192 Baud_Rate
BRL = 256 -
6
(1-SPD)
2SMOD1 FCK_SI 32 Baud_Rate
TH1 = 256 -
a. IBRG Formula
b. T1 Formula
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Table 76. Internal Baud Rate Generator Value
FCK_IDLE= 4 MHz Baud Rate 115200 57600 38400 19200 9600 4800 SPD 1 1 1 1 1 1 SMOD1 1 1 1 1 1 1 BRL 254 252 249 243 230 204 Error% 8.51 8.51 6.99 0.16 0.16 0.16 SPD 1 1 1 1 1 1 FCK_IDLE= 8 MHz SMOD1 1 1 1 1 1 1 BRL 252 247 243 230 204 152 Error% 8.51 3.55 0.16 0.16 0.16 0.16 SPD 1 1 1 1 1 1 FCK_IDLE= 9.6 MHz SMOD1 1 1 1 1 1 1 BRL 251 246 240 225 194 131 Error% 4.17 4.17 2.34 0.81 0.81 0.00
FCK_IDLE= 12 MHz Baud Rate 115200 57600 38400 19200 9600 4800 SPD 1 1 1 1 1 1 SMOD1 1 1 1 1 1 1 BRL 249 243 236 217 178 100 Error% 6.99 0.16 2.34 0.16 0.16 0.16 SPD 1 1 1 1 1 1
FCK_IDLE= 16 MHz SMOD1 1 1 1 1 1 1 BRL 247 239 230 204 152 48 Error% 3.55 2.12 0.16 0.16 0.16 0.16 SPD 1 1 1 1 1 1
FCK_IDLE= 24 MHz SMOD1 1 1 1 1 1 1 BRL 243 230 217 178 100 N/A Error% 0.16 0.16 0.16 0.16 0.16 N/A
Baud Rate Selection (Mode 2)
In mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of the peripheral clock frequency. As shown in Figure 81 the selection is done using SMOD1 bit in PCON register. Figure 82 gives the baud rate calculation formula depending on the selection. Figure 81. Baud Rate Generator Selection (Mode 2)
CK_ SI /2 0 1
16
To Serial Port
SMOD1
PCON.7
Figure 82. Baud Rate Formula (Mode 2)
Baud_Rate = 2SMOD1 FCK_SI 32
For mode 0 for UART, thanks to the bit M0SRC located in BDRCON register (Table 82)
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Registers
Table 77. Serial Control Register - SCON (98h)
7 FE/SM0 Bit 6 SM1 Bit 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 in PCON register must be set to enable access to the FE bit Serial port Mode bit 0 (SMOD0=1) Refer to SM1 for serial port mode selection. SMOD0 in PCON register must be cleared to enable access to the SM0 bit Serial port Mode bit 1 SM0 SM1 Mode 6 SM1 0 0 1 1 0 1 0 1 0 1 2 3 DescriptionBaud Rate Shift Register FCk_IDLE/6 8-bit UARTVariable 9-bit UARTFCK_IDLE /32 or /16 9-bit UARTVariable
FE 7 SM0
5
SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0.
4
REN
Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
3
TB8
Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8/Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 66 and Figure 67 in the other modes.
2
RB8
1
TI
0
RI
Reset Value = 0000 0000b (Bit addressable)
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Table 78. Slave Address Mask Register for UART - SADEN (B9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Table 79. Slave Address Register for UART - SADDR (A9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Table 80. Serial Buffer Register for UART - SBUF (99h)
7 6 5 4 3 2 1 0
Reset Value = XXXX XXXXb Table 81. Baud Rate Reload Register for the internal baud rate generator, UART - BRL (9Ah)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Table 82. Baud Rate Control Register - BDRCON - (9Bh)
7 Bit Number 7-5 6 5 4 BRR 3 TBCK 2 RBCK 1 SPD 0 M0SRC
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Transmission Baud rate Generator Selection bit for UART Cleared to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Reception Baud Rate Generator Selection bit for UART Cleared to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Baud Rate Speed Control bit for UART Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART
4
BRR
3
TBCK
2
RBCK
1
SPD
0
M0SRC
Cleared to select FCK_SI /6 as the Baud Rate Generator. Set to select the internal Baud Rate Generator for UART in mode 0.
Reset Value = XXX0 0000b (Not bit addressable)
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Serial Port Interface (SPI)
Features
Only for AT8xC5122. The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI module include the following: * * * * * * Full-duplex, three-wire synchronous transfers Master or Slave operation Eight programmable Master clock rates Serial clock with programmable polarity and phase Master Mode fault error flag with MCU interrupt capability Write collision flag protection
Signal Description
Figure 83 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices: Figure 83. Typical SPI Bus
MISO MOSI SCK SS
Slave 1 VDD
MISO MOSI SCK SS MISO MOSI SCK SS
Master
0 1 2 3
PORT
Slave 4
MISO MOSI SCK SS
Slave 3
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines.
Master Input Slave Output (MISO)
SPI Serial Clock (SCK)
MISO MOSI SCK SS
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Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. Only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port pins (Figure 83). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Section "Error Conditions", page 142). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: * The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin will be pulled low. Therefore, the MODF flag in the SPSTA will never be set (1). The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This kind of configuration can happen when the system comprises one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device.
*
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of six clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. Table 83 gives the different clock rates selected by SPR2:SPR1:SPR0 Table 83. SPI Master Baud Rate Selection
SPR2:SPR1:SPR0 000 001 010 011 100 101 110 111 Clock Rate Reserved FCK_SPI /4 FCK_SPI / 8 FCK_SPI /16 FCK_SPI /32 FCK_SPI /64 FCK_SPI /128 Reserved Baud Rate Divisor (BD) N/A 4 8 16 32 64 128 N/A
1. 2.
Clearing SSDIS control bit does not clear MODF. Special care should be taken not to set SSDIS control bit when CPHA = '0' because in this mode, the SS is used to start the transmission.
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Functional Description
Figure 84 shows a detailed structure of the SPI module. Figure 84. SPI Module Block Diagram
Internal Bus SPDAT IntClk Shift Register
7 6 5 4 3 2 1 0
Clock Divider
/4 /8 /16 /32 /64 /128
Receive Data Register
Pin Control Logic
MOSI MISO
Clock Logic Clock Select
M S
SCK SS
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI Control
8-bit bus 1-bit signal
SPI Interrupt Request
SPSTA
SPIF WCOL
-
MODF
-
-
-
-
Operating Modes
The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Salve mode. The configuration and initialization of the SPI module is made through one register: * * * * The Serial Peripheral Control register (SPCON) SPCON The Serial Peripheral Status register (SPSTA) The Serial Peripheral Data register (SPDAT) Once the SPI is configured, the data exchange is made using:
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 85).
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Figure 85. Full-duplex Master-Slave Interconnection
8-bit Shift Register
MISO MOSI
MISO MOSI SCK
8-bit Shift Register
SPI Clock Generator
SCK SS VDD
SS VSS
Master MCU
Slave MCU
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (3), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from the Slave on the Master's MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. When the pin SS is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the SPDAT is resent.
Slave Mode
The SPI operates in Slave mode when the Master bit, MSTR (4), in the SPCON register is cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to '0'. SS must remain low until the transmission is complete. In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module. After a byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another byte enters the shift register (5). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock Polarity (CPOL (6) ) and the Clock Phase (CPHA(4)). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 86 and Figure 87). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
3. 4. 5. 6.
The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI. The SPI module should be configured as a Slave before it is enabled (SPEN set). The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = '0').
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Figure 86. Data Transmission Format (CPHA = 0)
1 2 3 4 5 6 7 8
SCK Cycle Number SPEN (internal)
SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB
Figure 87. Data Transmission Format (CPHA = 1)
SCK Cycle Number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture point
1
2
3
4
5
6
7
8
MSB MSB
bit6 bit6
bit5 bit5
bit4 bit4
bit3 bit3
bit2 bit2
bit1 bit1
LSB LSB
As shown in Figure 86, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 88). Figure 88. CPHA/SS Timing
MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Byte 1 Byte 2 Byte 3
Figure 87 shows an SPI transmission in which CPHA is "1". In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmis-
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sions (Figure 88). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line. Error Conditions Mode Fault (MODF) The following flags in the SPSTA signal SPI error conditions. MODF error bit in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: * * * An SPI receiver/error CPU interrupt request is generated. The SPEN bit in SPCON is cleared. This disable the SPI. The MSTR bit in SPCON is cleared.
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes '0'. However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master is attempting to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin. Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. Overrun Condition An overrun condition occurs when the Master device tries to send several data bytes and the Slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost. This condition is not detected by the SPI peripheral. SS Error Flag ( SSERR ) A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit ( reset of the SPI state machine ). Two SPI status flags can generate a CPU interrupt requests: Table 84. SPI Interrupts
Flag SPIF (SP data transfer) MODF (Mode Fault) Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = '0')
Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests.
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Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. Figure 89 gives a logical view of the above statements. Figure 89. SPI Interrupt Requests Generation
SPIF MODF SPI Receiver/error CPU Interrupt Request SSDIS SPI Transmitter CPU Interrupt Request SPI CPU Interrupt Request
Registers Serial Peripheral Control Register (SPCON)
There are three registers in the module that provide control, status and data storage functions. These registers are describes in the following paragraphs. The Serial Peripheral Control Register does the following: * * * * * Selects one of the Master clock rates Configures the SPI module as Master or Slave Selects serial clock polarity and phase Enables the SPI module Frees the SS pin for a general-purpose
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Table 85. Serial Peripheral Control Register - SPCON (C3h)
7 SPR2 Bit Number 7 6 SPEN Bit Mnemonic SPR2 5 SSDIS R/W Mode RW 4 MSTR 3 CPOL 2 CPHA 1 SPR1 0 SPR0
Description Serial Peripheral Rate 2 Bit with SPR1 and SPR0 define the clock rate Serial Peripheral Enable
6
SPEN
RW
Clear to disable the SPI interface (internal reset of the SPI) Set to enable the SPI interface SS Disable
5
SSDIS
RW
Clear to enable SS in both Master and Slave modes Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA = '0' Serial Peripheral Master
4
MSTR
RW
Clear to configure the SPI as a Slave Set to configure the SPI as a Master Clock Polarity
3
CPOL
RW
Clear to have the SCK set to '0' in idle state Set to have the SCK set to '1' in idle low Clock Phase
2
CPHA
RW
Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL) Set to have the data sampled when the SPSCK returns to idle state (see CPOL) Serial Peripheral Rate (SPR2:SPR1:SPR0) 000: Reserved
1
SPR1
RW
001: FCK_SPI /4 010: FCK_SPI/8 011: FCK_SPI/16 100: FCK_SPI/32 101: FCK_SPI/64 110: FCK_SPI/128 111: Reserved
0
SPR0
RW
Reset Value = 00010100b
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Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following
conditions:
* * *
Data transfer complete Write collision Inconsistent logic level on SS pin (mode fault error)
7 SPIF Bit Number 6 WCOL Bit Mnemonic 5 SSERR 4 MODF 3 2 1 0 -
Table 86. Serial Peripheral Status and Control Register - SPSTA (C4h)
R/W Mode Description Serial Peripheral data transfer flag
7
SPIF
R
Clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. Write Collision flag
6
WCOL
R
Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. Synchronous Serial Slave Error flag
5
SSERR
R
Set by hardware when SS is modified before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). Mode Fault
4
MODF
R
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level
3-0
-
RW
Reserved The value read from this bit is indeterminate. Do not change these bits.
Reset Value = 00X0XXXXb
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Serial Peripheral DATa Register (SPDAT)
The Serial Peripheral Data Register (Table 87) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model. A read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 87. Serial Peripheral Data Register - SPDAT (C5h)
7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0
Bit Bit Number Mnemonic Description Receive data bits SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: 7-0 R7:0 Do not change SPR2, SPR1 and SPR0 Do not change CPHA and CPOL Do not change MSTR Clearing SPEN would immediately disable the peripheral Writing to the SPDAT will cause an overflow
Reset Value = XXXX XXXXb
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Timers/Counters
The AT8xC5122D implements two general-purpose, 16-bit Timers/Counters. Although they are identified as Timer 0, Timer 1, you can independently configure each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The Timer registers and associated control registers are implemented as addressable Special Function Registers (SFRs). Two of the SFRs provide programmable control of the Timers as follows: * Timer/Counter mode control register (TMOD) and Timer/Counter control register (TCON) control respectively Timer 0 and Timer 1.
The various operating modes of each Timer/Counter are described below.
Timer/Counter Operations
For example, a basic operation is Timer registers THx and TLx (x= 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in the TCON register (see Table 88 on page 152) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows, it increments THx and when THx overflows it sets the Timer overflow flag (TFx) in the TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but the TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down system clock or the external pin Tx as the source for the counted signal. The TRx bit must be cleared when changing the operating mode, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx#= 0), the Timer register counts the divided-down system clock. The Timer register is incremented once every peripheral cycle. Exceptions are the Timer 2 Baud Rate and Clock-Out modes in which the Timer register is incremented by the system clock divided by two. For Counter operation (C/Tx#= 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled during every S5P2 state. The Programmer's Guide describes the notation for the states in a peripheral cycle. When the sample is high in one cycle and low in the next one, the Counter is incremented. The new count value appears in the register during the next S3P1 state after the transition has been detected. Since it takes 12 states (24 oscillator periods) to recognize a negative transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle.
Timer 0
Timer 0 functions as either a Timer or an event Counter in four operating modes. Figure 90 through Figure 96 show the logic configuration of each mode. Timer 0 is controlled by the four lower bits of the TMOD register (see Table 89 on page 153) and bits 0, 1, 4 and 5 of the TCON register (see Table 88 on page 152). The TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and the operating mode (M10 and M00). The TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
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For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets the TF0 flag and generates an interrupt request. It is important to stop the Timer/Counter before changing modes. Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo-32 prescaler implemented with the lower five bits of the TL0 register (see Figure 90). The upper three bits of the TL0 register are indeterminate and should be ignored. Prescaler overflow increments the TH0 register. Figure 91 gives the overflow period calculation formula.
Figure 90. Timer/Counter x (x= 0 or 1) in Mode 0
FCK_Tx
/6
0 1
THx (8 bits)
TLx (5 bits)
Overflow
TFx
TCON reg
Timer x Interrupt Request
Tx
C/Tx#
TMOD reg
INTx# GATEx
TMOD reg
TRx
TCON reg
Figure 91. Mode 0 Overflow Period Formula
TFxPER =
6 (16384 - (THx, TLx))
FCK_Tx
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with the TH0 and TL0 registers connected in a cascade (see Figure 92). The selected input increments the TL0 register. Figure 93 gives the overflow period calculation formula when in timer mode.
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Figure 92. Timer/Counter x (x = 0 or 1) in Mode 1
FCK_Tx Timer x Interrupt Request
/6
0 1 C/Tx# TMOD reg
THx (8 bits)
TLx (8 bits)
Overflow
TFx TCON reg
Tx INTx# GATEx TMOD reg TRx TCON reg
Figure 93. Mode 1 Overflow Period Formula
TFxPER =
6 (65536 - (THx, TLx))
FCK_Tx
Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads Reload) from the TH0 register (see Figure 94). TL0 overflow sets the TF0 flag in the TCON register and reloads TL0 with the contents of TH0, which is preset by the software. When the interrupt request is serviced, the hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to the TH0 register. Figure 95 gives the autoreload period calculation formula when in timer mode. Figure 94. Timer/Counter x (x = 0 or 1) in Mode 2
FCK_Tx
/6
0 1 C/Tx# TMOD reg
TLx (8 bits)
Overflow
Tx
TFx TCON reg
Timer x Interrupt Request
INTx# GATEx TMOD reg TRx TCON reg
THx (8 bits)
Figure 95. Mode 2 Autoreload Period Formula
TFxPER= 6 (256 - THx) FCK_Tx
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Mode 3 (Two 8-bit Timers)
Mode 3 configures Timer 0 so that registers TL0 and TH0 operate as 8-bit Timers (see Figure 96). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in the TMOD register, and TR0 and TF0 in the TCON register in the normal manner. TH0 is locked into a Timer function (counting FUART) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3. Figure 97 gives the autoreload period calculation formulas for both TF0 and TF1 flags. Figure 96. Timer/Counter 0 in Mode 3: Two 8-bit Counters
FCK_T0
/6
0 1 C/T0# TMOD.2
TL0 (8 bits)
Overflow
T0
TF0 TCON.5
Timer 0 Interrupt Request
INT0# GATE0 TMOD.3 FCK_T0 /6 TR1 TCON.6 TR0 TCON.4 TH0 (8 bits) Overflow TF1 TCON.7
Timer 1 Interrupt Request
Figure 97. Mode 3 Overflow Period Formula
TF0PER = 6 (256 - TL0) FCK_T0 TF1PER = 6 (256 - TH0) FCK_T0
Timer 1
Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The following comments help to understand the differences: * Timer 1 functions as either a Timer or an event Counter in three operating modes. Figure 90 through Figure 94 show the logical configuration for modes 0, 1, and 2. Mode 3 of Timer 1 is a hold-count mode. Timer 1 is controlled by the four high-order bits of the TMOD register (see Table 89 on page 153) and bits 2, 3, 6 and 7 of the TCON register (see Table 88 on page 152). The TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and the operating mode (M11 and M01). The TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and the interrupt type control bit (IT1). Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag and generates an interrupt request.
*
* *
*
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* When Timer 0 is in mode 3, it uses Timer 1's overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. It is important to stop the Timer/Counter before changing modes.
* Mode 0 (13-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 90). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments the TH1 register. Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 92). The selected input increments the TL1 register.
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from Reload) the TH1 register on overflow (see Figure 94). TL1 overflow sets the TF1 flag in the TCON register and reloads TL1 with the contents of TH1, which is preset by the software. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when the TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
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Registers
Timer/Counter Control Register Table 88. TCON (S:88h)
7 TF1 Bit Number 7 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
Bit Mnemonic Description TF1 Timer 1 Overflow flag Cleared by the hardware when processor vectors interrupt routine. Set by the hardware when Timer 1 register overflows. Timer 1 Run Control bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. Timer 0 Overflow flag Cleared by the hardware when processor vectors interrupt routine or by software when the interrupt is disabled Set by the hardware when Timer 0 register overflows. Timer 0 Run Control bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. Interrupt 1 Edge flag Cleared by the hardware when interrupt is processed if edge-triggered (see IT1). Set by the hardware when external interrupt is detected on the INT1# pin. Interrupt 1 Type Control bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. Interrupt 0 Edge flag Cleared by the hardware when interrupt is processed if edge-triggered (see IT0). Set by the hardware when external interrupt is detected on INT0# pin. Interrupt 0 Type Control bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Reset Value = 0000 0000b
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Table 89. Timer/Counter Mode Control Register - TMOD (S:89h)
7 GATE1 Bit Number 7 6 C/T1# Bit Mnemonic GATE1 5 M11 Description Timer 1 Gating Control bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Timer 1 Counter/Timer Select bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. Timer 1 Mode Select bits M11 M01 Operating mode 0 0 Mode 0:8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1:16-bit Timer/Counter. 1 0 Mode 2:8-bit auto-reload Timer/Counter (TL1). Reloaded from TH1 at overflow. 1 1 Mode 3:Timer 1 halted. Retains count. Timer 0 Gating Control bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Timer 0 Counter/Timer Select bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. Timer 0 Mode Select bit M10 M00 Operating mode 0 0 Mode 0:8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1:16-bit Timer/Counter. 1 0 Mode 2:8-bit auto-reload Timer/Counter (TL0). Reloaded from TH0 at overflow. 1 1 Mode 3:TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1's TR0 and TF0 bits. 4 M01 3 GATE0 2 C/T0# 1 M10 0 M00
6 5
C/T1# M11
4
M01
3
GATE0
2 1
C/T0# M10
0
M00
Reset Value = 0000 0000b
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Table 90. Timer 0 High Byte Register - TH0 (S:8Ch)
7 6 5 4 3 2 1 0
Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0
Reset Value = 0000 0000b Table 91. Timer 0 Low Byte Register - TL0 (S:8Ah)
7 6 5 4 3 2 1 0
Bit Number 7:0
Bit Mnemonic Description Low Byte of Timer 0
Reset Value = 0000 0000b Table 92. Timer 1 High Byte Register - TH1 (S:8Dh)
7 6 5 4 3 2 1 0
Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 1
Reset Value = 0000 0000b Table 93. Timer 1 Low Byte Register - TL1 (S:8Bh)
7 6 5 4 3 2 1 0
Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1
Reset Value = 0000 0000b
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Keyboard Interface
Introduction
Only for AT8xC5122. The AT8xC5122/23 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P5 and allow to exit from idle and power-down modes. The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 96 on page 158), KBE, The Keyboard interrupt Enable register (Table 95 on page 157), and KBF, the Keyboard Flag register (Table ). The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit ( KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 98). As detailed in Figure 99 each keyboard input has the capability to detect a programmable level according to KBLS.x bit value. Level detection is then reported in interrupt flags KBF.x that can be masked by software using KBE.x bits. This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allows usage of P5 inputs for other purpose. The KBF.x flags are set by hardware when an active level is on input P5.x. They are automatically reset after any read access on KBF. If the content of KBF must be analyzed, the first read instruction must transfer KBF contend to another location. The KBF register cannot be written by software. Figure 98. Keyboard Interface Block Diagram
P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 Input Circuitry Input Circuitry Input Circuitry Input Circuitry KBDIT Input Circuitry Input Circuitry Input Circuitry Input Circuitry EKB
IEN1.0
Description
Interrupt
Keyboard Interface Interrupt Request
Figure 99. Keyboard Input Circuitry
0 1
P5.x
KBF.x KBE.x
KBLS.x
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Power Reduction Mode
P5 inputs allow exit from idle and power-down modes as detailed in Section "PowerDown Mode".
Registers
Table 94. Keyboard Flag Register - KBF (9Eh)
7 KBF7 Bit Number 6 KBF6 Bit Mnemonic 5 KBF5 4 KBF4 3 KBF3 2 KBF2 1 KBF1 0 KBF0
Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBE.7 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard line 6 flag Set by hardware when the Port line 6 detects a programmed level. It generates a Keyboard interrupt request if the KBE.6 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard line 5 flag Set by hardware when the Port line 5 detects a programmed level. It generates a Keyboard interrupt request if the KBE.5 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard line 4 flag Set by hardware when the Port line 4 detects a programmed level. It generates a Keyboard interrupt request if the KBE.4 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard line 3 flag Set by hardware when the Port line 3 detects a programmed level. It generates a Keyboard interrupt request if the KBE.3 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard line 2 flag Set by hardware when the Port line 2 detects a programmed level. It generates a Keyboard interrupt request if the KBE.2 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard line 1 flag Set by hardware when the Port line 1 detects a programmed level. It generates a Keyboard interrupt request if the KBE.1 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a Keyboard interrupt request if the KBE.0 bit in KBE register is set. Cleared by hardware after the read of the KBF register.
7
KBF7
6
KBF6
5
KBF5
4
KBF4
3
KBF3
2
KBF2
1
KBF1
0
KBF0
Reset Value = 0000 0000b
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Table 95. Keyboard Input Enable Register - KBE (9Dh)
7 KBE7 Bit Number 7 6 KBE6 Bit Mnemonic KBE7 5 KBE5 4 KBE4 3 KBE3 2 KBE2 1 KBE1 0 KBE0
Description Keyboard line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. Keyboard line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.6 bit in KBF register to generate an interrupt request. Keyboard line 5 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.5 bit in KBF register to generate an interrupt request. Keyboard line 4 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.4 bit in KBF register to generate an interrupt request. Keyboard line 3 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.3 bit in KBF register to generate an interrupt request. Keyboard line 2 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.2 bit in KBF register to generate an interrupt request. Keyboard line 1 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.1 bit in KBF register to generate an interrupt request. Keyboard line 0 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.0 bit in KBF register to generate an interrupt request.
6
KBE6
5
KBE5
4
KBE4
3
KBE3
2
KBE2
1
KBE1
0
KBE0
Reset Value = 0000 0000b
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Table 96. Keyboard Level Selector Register - KBLS (9Ch)
7 KBLS7 Bit Number 7 6 KBLS6 5 KBLS5 4 KBLS4 3 KBLS3 2 KBLS2 1 KBLS1 0 KBLS0
Bit Mnemonic Description KBLS7 Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. Keyboard line 5 Level Selection bit Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. Keyboard line 4 Level Selection bit Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. Keyboard line 3 Level Selection bit Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. Keyboard line 2 Level Selection bit Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. Keyboard line 1 Level Selection bit Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0.
6
KBLS6
5
KBLS5
4
KBLS4
3
KBLS3
2
KBLS2
1
KBLS1
0
KBLS0
Reset Value = 0000 0000b
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Interrupt System
Introduction
The AT8xC5122/23 implements an interrupt controller with 15 inputs but only 9 are used for : - - - - - - - two external interrupts (INT0 and INT1) two timer interrupts (timers 0, 1), the UART interface the SPI interface the keyboard interface the USB interface the Smart Card Interface.
Interrupt System Description
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable registers (Table 98 on page 162 and Table 99 on page 163). These registers also contain a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority Low registers (Table 101 on page 164 and Table 103 on page 166) and in the Interrupt Priority High register (Table 102 on page 165 and Table 105 on page 168) shows the bit values and priority levels associated with each combination. A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced first. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 97. Priority Level Bit Values
IPH.x 0 0 1 1 IPL.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest)
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Figure 100. Interrupt Control System
0 1 IT0 TCON.0 TF0 TCON.5 RXD RXEN ISEL.0 INT1 1 0 OELEV ISEL.3 0 1 CPLEV PRESEN ISEL.7 ISEL.1 TF1 TCON.7 RXD RI SCON.0 TI SCON.1 KBFx EKB (1) IEN1.0 00 01 10 11 ESPI (1) IEN1.2 00 01 10 11 00 01 10 11 EA IEN0.7 IPH/L Priority Enable Lowest Priority Interrupts ET1 IEN0.3 OEEN ISEL.2 0 1 IT1 TCON.2 IE1 TCON.3 EX1 IEN0.2 00 01 10 11 RXIT ISEL.4 ET0 IEN0.1 00 01 10 11 EX0 IEN0.0 Highest Priority Interrupts
INT0#
IE0
TCON.1
00 01 10 11
CPRES
PRESIT ISEL.5 00 01 10 11 00 01 10 11 00 01 10 11
TXD
SERIAL INTERFACE CONTROLLER
P5.x
0 1 KBLSx
ES IEN0.4
KBEx
MISO MOSI SCK SMART CARD INTERFACE CONTROLLER ESCI IEN1.3 D+ DUSB CONTROLLER EUSB IEN1.6 note (1) : Not applicable to AT83C5123 SPI CONTROLLER (1)
CIO CCLK
Interrupt Enable
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INT1 Interrupt Vector The INT1 interrupt is multiplexed with the following three inputs: * * * INT1 : Standard 8051 interrupt input RXD : Received data on UART CPRES: Insertion or remove of the main card
The setting configurations for each input is detailed below. INT1 Input This interrupt input is active under the following conditions : * * * It must be enabled by OEEN Bit (ISEL Register) It can be active on a level or falling edge following IT1 Bit (TCON Register) status If level triggering selection is set, the active level 0 or 1 can be selected with OELEV Bit (ISEL Register)
The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is cleared when interrupt is processed. RXD Input A second vector interrupt input is the reception of a character. UART Rx input can generate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA must also be set. Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on P3.0/RXD input. CPRES Input The third input is the detection of a level change on CPRES input (P1.2). This input can generate an interrupt if enabled with PRESEN (ISEL.1) , EX1 (IE0.2) and EA (IE0.7) Bits. This detection is done according to the level selected with Bit CPLEV (ISEL.7). Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are met. This Bit must be cleared by software.
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Registers
Table 98. Interrupt Enable Register 0 - IEN0 (A8h)
7 EA Bit Number 7 6 Bit Mnemonic Description Enable All interrupt bit EA Cleared to disable all interrupts. Set to enable all interrupts. Reserved The value read from this bit is indeterminate. Do not change these bits. Serial port Enable bit 4 ES Cleared to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Cleared to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit 2 EX1 Cleared to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit 1 ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit 0 EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. 5 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
6-5
-
3
ET1
Reset Value = 0000 0000b (Bit addressable)
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Table 99. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC5122
7 Bit Number 7 6 EUSB Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Enable bit 6 EUSB Cleared to disable USB interrupt . Set to enable USB interrupt. Reserved The value read from this bit is indeterminate. Do not change these bits. SCI interrupt Enable bit Cleared to disable SCIinterrupt . Set to enable SCI interrupt. SPI interrupt Enable bit Cleared to disable SPI interrupt . Set to enable SPI interrupt. Reserved The value read from this bit is indeterminate. Do not change this bit. Keyboard interrupt Enable bit Cleared to disable keyboard interrupt . Set to enable keyboard interrupt. 5 4 3 ESCI 2 ESPI 1 0 EKB
5-4
-
3
ESCI
2
ESPI
1
-
0
EKB
Reset Value = X0XX 00X0b (Bit addressable)
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Table 100. Interrupt Enable Register 1 - IEN1 (B1h) for AT83C5123
7 Bit Number 7 6 EUSB Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Enable bit 6 EUSB Cleared to disable USB interrupt . Set to enable USB interrupt. Reserved The value read from this bit is indeterminate. Do not change these bits. SCI interrupt Enable bit Cleared to disable SCIinterrupt . Set to enable SCI interrupt. Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change this bit. 5 4 3 ESCI 2 1 0
5-4
-
3
ESCI
2 1 0
Reset Value = X0XX 0XXXb (Bit addressable)
Table 101. Interrupt Priority Low Register 0 - IPL0 (B8h)
7 Bit Number 7-5 4 3 2 1 0 6 Bit Mnemonic Description PSL PT1L PX1L PT0L PX0L Reserved The value read from this bit is indeterminate. Do not change these bits. Serial port Priority bit Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level. 5 4 PSL 3 PT1L 2 PX1L 1 PT0L 0 PX0L
Reset Value = X000 0000b (Bit addressable)
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Table 102. Interrupt Priority High Register 0 - IPH0 (B7h)
7 Bit Number 7-5 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. Serial port Priority High bit 4 PSH PSH 0 0 1 1 PT1H 0 0 1 1 PX1H 0 0 1 1 PT0H 0 0 1 1 PX0H 0 0 1 1 PSL 0 1 0 1 PT1L 0 1 0 1 PX1L 0 1 0 1 PT0L 0 1 0 1 PX0L 0 1 0 1 Priority Level Lowest 5 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
Highest Priority Level Lowest
Timer 1 overflow interrupt Priority High bit 3 PT1H
Highest Priority Level Lowest
External interrupt 1 Priority High bit 2 PX1H
Highest Priority Level Lowest
Timer 0 overflow interrupt Priority High bit 1 PT0H
Highest Priority Level Lowest
External interrupt 0 Priority High bit 0 PX0H
Highest
Reset Value = X000 0000b (Not bit addressable)
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Table 103. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT8xC5122
7 Bit Number 7 6 5-4 3 2 1 0 6 PUSBL Bit Mnemonic Description PUSBL PSCIL PSPIL PKBL Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priority bit Refer to PUSBH for priority level. Reserved The value read from this bit is indeterminate. Do not change these bits. SCI Interrupt Priority bit Refer to PSPIH for priority level. SPI Interrupt Priority bit Refer to PSPIH for priority level. Reserved The value read from this bit is indeterminate. Do not change this bit. Keyboard Interrupt Priority bit Refer to PKBDH for priority level. 5 4 3 PSCIL 2 PSPIL 1 0 PKBDL
Reset Value = X00X 00X0b (Bit addressable)
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Table 104. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT83C5123
7 Bit Number 7 6 5-4 3 2 1 0 6 PUSBL Bit Mnemonic Description PUSBL PSCIL Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priority bit Refer to PUSBH for priority level. Reserved The value read from this bit is indeterminate. Do not change these bits. SCI Interrupt Priority bit Refer to PSPIH for priority level. Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change this bit. 5 4 3 PSCIL 2 1 0
Reset Value = X0XX 0XXXb (Bit addressable)
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Table 105. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC5122
7 Bit Number 7 6 PUSBH Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priotity High bit PUSBH PUSBL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Reserved The value read from this bit is indeterminate. Do not change these bits. SCI Interrupt Priority High bit 3 PSCIH PSCIH 0 0 1 1 PSPIH 0 0 1 1 PSCIL 0 1 0 1 PSPIL 0 1 0 1 Priority Level Lowest 5 4 3 PSCIH 2 1 0
6
PUSBH
5-4
-
Highest Priority Level Lowest
SPI Interrupt Priority High bit 2 PSPIH
Highest
1
-
Reserved The value read from this bit is indeterminate. Do not change this bit. Keyboard Interrupt Priority High bit PKBDH 0 0 1 1 PKBDL 0 1 0 1 Priority Level Lowest
0
PKBH
Highest
Reset Value = XXXX X000b (Not bit addressable)
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Table 106. Interrupt Priority High Register 1 - IPH1 (B3h) for AT83C5123
7 Bit Number 7 6 PUSBH Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priotity High bit PUSBH PUSBL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Reserved The value read from this bit is indeterminate. Do not change these bits. SCI Interrupt Priority High bit 3 PSCIH PSCIH 0 0 1 1 PSCIL 0 1 0 1 Priority Level Lowest 5 4 3 PSCIH 2 1 0 -
6
PUSBH
5-4
-
Highest
2 1 0 -
Reserved The value read from this bit is indeterminate. Do not change these bits. Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change these bits.
Reset Value = X0XX 0XXXb (Not bit addressable)
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Table 107. Interrupt Enable Register - ISEL (S:A1h)
7 CPLEV Bit Number 6 Bit Mnemonic Description Card presence detection level 7 CPLEV This bit indicates which CPRES level will bring about an interrupt Set this bit to indicate that Card Presence IT will appear if CPRES is at high level. Clear this bit to indicate that Card Presence IT will appear if CPRES is at low level. 6 Reserved The value read from this bit is indeterminate. Do not change this bit. Card presence detection interrupt flag 5 PRESIT Set by hardware Must be cleared by software Received data interrupt flag 4 RXIT Set by hardware Must be cleared by software 3 OELEV INT1 signal active level Set this bit to indicate that high level is active. Clear this bit to indicate that low level is active. INT1 Interrupt Disable bit 2 OEEN Clear to disable INT1 interrupt Set to enable INT1 interrupt Card presence detection Interrupt Enable bit 1 PRESEN Clear to disable the card presence detection interrupt coming from SCIB. Set to enable the card presence detection interrupt coming from SCIB. Received data Interrupt Enable bit 0 RXEN Clear to disable the RxD interrupt. Set to enable the RxD interrupt (a minimal bit width of 100 s is required to wake up from power-down) . 5 PRESIT 4 RXIT 3 OELEV 2 OEEN 1 PRESEN 0 RXEN
Reset Value = 0000 0000b
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Interrupt Sources and Vectors
Table 108. Interrupt Vectors
Interrupt Source
Reset INT0 Timer 0 INT1 Timer 1 UART Reserved Reserved Keyboard Controller (1) Reserved SPI Controller (1) Smart Card Controller Reserved Reserved USB Controller Reserved
Polling Priority at Same Level
0 (Highest Priority) 1 2 3 4 6 7 5 8 9 10 11 12 13 14 15 (Lowest Priority)
Vector Address
C:0000h C:0003h C:000Bh C:0013h C:001Bh C:0023h C:002Bh C:0033h C:003Bh C:0043h C:004Bh C:0053h C:005Bh C:0063h C:006Bh C:0073h
Note:
1. Only fot AT8xC5122
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Microcontroller Reset
Introduction
The internal reset is used to start up (cold reset) or to re-start (warm reset) the microcontroller activity. When the reset is applied (active state), all internal registers are initialized so that the microcontroller starts from a known and clean state for the program always runs as expected. The reset is released (inactive state) when the following conditions are internally met : - - - The power supply has reatched a minimum level which garantees that the microcontroller works properly The on-chip oscillator has reached a minimum oscillation level which ensures a good noise to signal ratio and a correct internal duty cycle the active state duration is at least two machine cycles.
If one of the above conditions is not met the microcontroller is not correctly reset and might not work properly. The internal reset comes from four different sources : - - - - Reset pin Power On Reset (POR) Power Fail Detector (PFD) Hardware Watch-Dog Timer (WDT)
Figure 101. Reset bock diagram
Vcc
3.3V Internal Digital Regulator POR PFD C51 Core VCore
Watch Dog Timer
Internal Reset
RST
Microcontroller
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Power On Reset (POR)
The role of the POR is to monitor the power supply rise of the microcontroller core and release the internal reset only when the internal voltage exceeds the VPFDP threshold from which the microcontroller core is stable (see Figure 102). This feature replaces the external reset function and therefore avoid the use of external components on the reset pin. The role of the PFD is to monitor the power supply falls during a steady state condition in order to suspend the microcontroller and peripherals activity as soon as the power supply drops below the VPFDM threshold from which the microcontroller's core might become instable (see Figure 102). The PDF suspends the microcontroller's activity by holding the microcontroller under a reset state to avoid an unpredictable behaviour. A filter prevents the system from reseting when glitches lower than 50 ns duration are carried on Vcore. See Figure 102 and Figure 103 on page 174.
Power Fail Detector (PFD)
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Figure 102. Static behaviour of POR and PFD VCore VPFDP VPFDM
POR
Internal Reset 1
0
Figure 103. Dynamic behaviour of POR and PFD VCore VPFDP VPFDM t<50ns t>50ns
POR
PFD
t
POR
Internal Reset 1
0
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POR
PFD
t
AT8xC5122/23
Reset pin
As explained in the POR section there is no need to use the reset pin as the internal reset function at power up is ensured by the POR. Anyway, if some applications requires a long reset, a reset controlled by the user or a reset controlled by external superviser device, the use of the reset pin is necessary. As the pad integrates an internal pull-up of 10K, only an external capacitor of at least 10 F is required to have an impact on the reset duration. Figure 104. Long Reset Vcc
Long Reset
10 K
RST
Internal Reset
10 F
Microcontrolleur
Reset Controlled by the User
The external capacitor is not needed if no long reset is required. Figure 105. Reset Controlled by the User Vcc
10 K
RST
Internal Reset
Microcontrolleur
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Reset Controlled by an External Superviser Device
As the reset pin can be forced in output by the Watch-Dog timer (WDT) or the POR/PFD features, there can be a conflict between the external superviser device and the microcontroller's reset pin when in one side the external superviser is pulling the reset pin to VCC and in another side the WDT or POR/PFD features tries to force the reset pin to ground. Therefore, it recommended to insert a series resistor of 1.8K +/-10% or a diode (1N4148 for instance) between the external superviser device and the reset pin as detailed in the following figures. Figure 106. Use of an External Serial Resistor
Microcontrolleur
Vcc
10 K
Superviser device Power On Reset Power Fail Detector Watchdog Timer
1.8 K
RST
To other on-board circuitry
Figure 107. Use of an External Diode
Microcontrolleur
Vcc
10 K RST
Power On Reset Power Fail Detector Watchdog Timer
1N4148
Superviser device
To other on-board circuitry
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Watchdog Timer
The AT8xC5122/23 microcontrollers contain a powerfull programmable hardware Watchdog Timer (WDT) that automatically resets the chip if its software fails to reset the WDT before the selected time interval has elapsed. It permits large timeout ranking from 4ms to 524ms @ FCK_WD = 24 MHz / X2 This WDT consist of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programmation (WDTPRG) register. When exiting the reset, the WDT is, by default, disabled. To activate the WDT, the user has to write the sequence 1EH and E1H into WDRST register. When the Watchdog Timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. The WDT is controlled by two registers (WDTRST and WDTPRG). Figure 108. Watchdog Timer
RESET WR WDTRST
Decoder
Control
Enable 14-bit COUNTER 7 - bit COUNTER Outputs
FCK_WD
-
-
-
-
-
2
1
0 RESET
WDTPRG
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Table 109. Watchdog Timer Out Register - WDTPRG (0A7h)
7 Bit Number 7-3 2 1 0 6 Bit Mnemonic S2 S1 S0 Description Reserved The value read from this bit is indeterminate. Do not change these bits. WDT Time-out select bit 2 WDT Time-out select bit 1 WDT Time-out select bit 0 5 4 3 2 S2 1 S1 0 S0
Reset Value = XXXX X000b The three lower bits (S0, S1, S2) located into WDTPRG register enables to program the WDT duration. Table 110. Machine Cycle Count
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Machine Cycle Count 214 - 1 215 - 1 216 - 1 217 - 1 218 - 1 219 - 1 220 - 1 221 - 1
To compute WD Timeout, the following formula must be applied: Time Out = 6 * (214 * 2 Svalue - 1 ) / FCK_WD
Note: Svalue represents the decimal value of (S2 S1 S0)
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Table 111. Timeout value for FCK_WD = 24 MHz / X2
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Timeout for FCK_WD= 24 MHz / X2 4.10 ms 8.19 ms 16.38 ms 32.77 ms 65.54 ms 131.07 ms 262.14 ms 524.29 ms
Table 112. Watchdog Timer Enable register (Write Only) - WDTRST (A6h)
7 6 5 4 3 2 1 0 -
Reset Value = XXXX XXXXb The WDTRST register is used to reset / enable the WDT by writing 1EH then E1H in sequence.
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Power Management
Before activating the Idle Mode or Power Down Mode, the CPU clock must be switched to on-chip oscillator source if the PLL is used to fed the CPU clock.
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high level. There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
Power Down Mode
To save maximum power, a power-down mode can be invoked by software (see Table 13, PCON register). WARNING: To minimize power consumption, all peripherals and I/Os with static current consumption must be set in the proper state. I/Os programmed with low speed output configuration (KB_OUT) must be switch to push-pull or Standard C51 configuration before entering power-down. The CVCC generator must also be switch off. In power-down mode, the oscillator is stopped and the instruction that invoked powerdown mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from powerdown. To properly terminate power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 , INT1, Keyboard, Card insertion/removal and USB Interrupts are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power-down mode, 1024 clocks are necessary to exit to power-down mode and enter in operating mode. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 109. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power-down exit will be completed when the first input is released. In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT8xC5122/23 into power-down mode.
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Figure 109. Power-down Exit Waveform
INT0 INT1 XTAL1
Active phase
Power-down phase
Oscillator restart phase
Active phase
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
Note: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered.
Table shows the state of ports during idle and power-down modes. Table State of Ports
Mode Idle Idle Power-down Power-down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 P0 Port Data(1) Floating Port Dat* Floating P1 Port Data Port Data Port Data Port Data P2 Port Data Address Port Data Port Data P3 Port Data Port Data Port Data Port Data P4 Port Data Port Data Port Data Port Data P5 Port Data Port Data Port Data Port Data
Note:
1. Port 0 can force a 0 level. A "one" will leave port floating.
Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high.
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USB Interface
Suspend The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active. The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-up event is detected. The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit in the USBCON register. 2. If CPU clock is fed from PLL, the on-chip oscillator must be selected to fed the CPU clock. 3. Disable the PLL by clearing the PLLEN bit in the PLLCON register. Resume When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated.
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Figure 110. Example of a Suspend/Resume Management
USB Controller Init SPINT Detection of a SUSPEND State Clear SPINT Set SUSPCLK Disable PLL
microcontroller in power-down
Put the USB pads in power down mode
Detection of a RESUME State Note : WUPCPU bit must be Cleared before enabling the PLL
WUPCPU
Clear SUSPCLK Clear WUPCPU bit Enable PLL
Smart Card Interface
Entering in Power-down Mode In order to reduce the power consumption, a power-down or idle mode can be invoked by software (see Table 13, PCON register). Before activating these modes the application will need to: Power-off the Smart Card Interface by applying the following sequence: * * * * Set CRST pin at low level by clearing the bit CARDRST in SCCON register. Set CCLK pin at low level by clearing the bit CLK then the CARDCLK in SCCON register. Set CIO pin at low level by clearing the bit UART in SCICR register then the bit CARDIO in SCCON register. Power the Smart Interface off by clearing the CARDVCC bit in SCCON register. This instruction enables to switch DC/DC converter off.
CPRES input: * * * * * Exiting from Power-down Mode Set the bit PRSEN in ISEL register Set the bit EX1 in IE0 register Set the bit EA in the IE0 register Invert the bit CPLEV in ISEL register (INT1 interrupt vector) Clear the bit PRESIT in the ISEL register
The microcontroller will exit from Power-down or Idle modes upon a reset or INT1 interrupt which is a multiplexing of the interruptions generated by the CPRES pin (Card detection), RxD flag (UART reception) and INT1 pin. 183
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Keyboard Interface
The keyboard interface applies only to AT8xC5122 version.
Entering in Power-down Mode In order to reduce the power consumption, the microcontroller can be set in power-down or idle mode by software (see Table 13, PCON register). Before activating these modes the application will need to configure the keyboard interface as follows: * Set all keyboard's ouputs pins KB Rx at low level by writing a 0 on the ports. This operation has a double effect: - - Exiting from Power-down Mode any key that is pressed generates an interrupt capable of waking-up the microcontroller, Set all bits KBE.x in KBE registers to enable interrupts.
The microcontroller will exit from Power-down Mode upon a reset or any interrupt generated by a key press. Note that 1024 clocks are necessary to exit from power-down mode when a keyboard interrupt occurs. This means that there will be a delay between the time at which the key is pressed and the time at which the application is able to identify the key.
Watchdog Timer during Power-down and Idle Mode
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode the user does not need to service the WDT. There are 2 methods of exiting Power-down mode : by a hardware reset or by a level activated external interrupt which is enabled prior to entering power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever AT8xC5122D is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting while the microcontroller is in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
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Registers
Table 113. Power Control Register - PCON (S:87h)
7 SMOD1 Bit Number 7 6 SMOD0 Bit Mnemonic SMOD1 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
Description Serial port Mode bit 1 for UART Set to select double baud rate in mode 1,2 or 3 Serial port Mode bit 0 for UART
6
SMOD0
Cleared to select SM0 bit in SCON register Set to select FE bit in SCON register
5
-
Reserved The value read from this bit is indeterminate. Do not change this bit. Power-Off Flag (Only for ROM version parts) Cleared to recognize next reset type
4
POF
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software Warning : in CRAM and FLASH versions, this bit is reserved. General purpose Flag
3
GF1
Cleared by user for general-purpose usage Set by user for general-purpose usage General purpose Flag
2
GF0
Cleared by user for general-purpose usage Set by user for general-purpose usage Power-Down mode bit
1
PD
Cleared by hardware when reset occurs Set to enter power-down mode Idle mode bit
0
IDL
Cleared by hardware when interrupt or reset occurs Set to enter idle mode
Reset Value = 00X1 0000b Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn't affect the value of this bit.
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Electrical Characteristics
Absolute Maximum Ratings
Ambiant Temperature Under Bias ......................-25C to 85C Storage Temperature .................................... -65C to + 150C Voltage on VCC to VSS ......................................-0.5 V to + 6.0V Voltage on Any Pin to VSS........................-0.5 V to VCC + 0.5 V Power Dissipation 1 W Note: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package.
DC Parameters
TA = -40 to +85C; VSS = 0 V, FCK_CPU= 0 to 24 MHz , VCC = 3.6V to 5.5V
Symbol VIL VIH VIH1 VOL VOH VOL1 VOH1 IIL ILI ITL RMEDIUM RWEAK CIO DVCC DICC VPFDP VPFDM trise, tfall Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage: P0, ALE, PSEN Output High Voltage: P0, ALE, PSEN Output Low Voltage: P2, P3, P4, P5, P1.2, P1.6, P1.7 Output High Voltage: P2, P3, P4, P5, P1.2, P1.6, P1.7 Logical 0 Input Current ports 2 to 5 and P1.2, P1.6, P1.7, if Weak pull-up enabled Input Leakage Current Logical 1 to O transistion Current, Port 51 configuration Medium Pullup Resistor Weak Pullup Resistor Capacitance of I/O Buffer Digital Supply Voltage Digital Supply Output Current (DVcc pin) Power Fail High Level Threshold Power Fail Low Level Threshold VDD rise and fall time 2,5 1s 2.8 2.6 600 3 3.4 10 100 10 3.6 10 3 0.9 VCC -50 10 -650 0.9 VCC 0.45 Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 Unit V V V V V V V A A A k k pF V mA V V second Fc = 1MHz TA = 25C CL = 470 nF CL = 100 nF FCK_CPU = 24 MHz IOL = 1.6 mA IOH = 10 A IOL = 0.8 mA IOH = -10 A Vin = 0.45 V 0.45 V < VIN < VCC VIN = 2 V Test Conditions
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Symbol RRST IPD ICCIDLE ICCOP ICCOP ICCOP ICCWRITE ICCOP ICCOP ICCOP ICCWRITE Parameter Internal reset pull-up resistor Power down consumption Power Supply current in IDLE mode Power Supply current in Active mode (AT89C5122) with DC/DC ON Power Supply current in Active mode (AT85C5122) with DC/DC ON Power Supply current in Active mode (AT83C5122) with DC/DC ON Power Supply current in Active mode (AT89C5122) Flash or E2PROM write DC/DC ON Power Supply current in Active mode (AT89C5122) with DC/DC OFF Power Supply current in Active mode (AT85C5122) with DC/DC FF Power Supply current in Active mode (AT83C5122) with DC/DC OFF Power Supply current in Active mode (AT89C5122) Flash or E2PROM write DC/DC OFF Min 5 Typ 10 60A 40A Max 30 200A 200A 0.4*F+2 1.6*F+3 1.6*F+3 1.6*F+2 1.6*F+4 0.8*F+3 0.8*F+3 0.8*F+2 0.8*F+4 mA mA mA mA mA mA mA mA mA Unit k Vcc = 5.5V Vcc = 3.6V Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Vcc = 5.5V (F in MHz) Test Conditions
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ICC Current Test Conditions
Figure 111. Power Down Mode
All other pins are disconnected. VCC Ipd
LI VCC AVCC P0
VCC
VCC (NC)
GND XTAL2 XTAL1 Vss EA PLLF AVss GND GND
GND
Figure 112. Active and Idle Mode
All other pins are disconnected. VCC Icc
LI VCC AVCC P0
VCC
VCC (NC) CLOCK SIGNAL
XTAL2 XTAL1 Vss EA PLLF AVss GND GND
GND
LED's
Symbol Parameter Min 1 IOL Output Low Current, P3.6 and P3.7 LED modes 2 5 Typ 3 6 10 Max 5 8 20 Unit mA mA mA Test Conditions 2 mA configuration 4 mA configuration 10 mA configuration
Note:
1. (TA = -20C to +50C, VCC - VOL = 2 V )
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Smart Card Interface
Card VCC 5V (for IEC7816-3 Class A cards)
Symbol Vcc CICC_ovf CVCC Parameter Power Supply Card Supply Current overflow Card Supply Voltage Ripple on Card Voltage 4.6 Min 4.0 100 5.4 200 Typ Max 5.5 Unit V mA V mV CICC = 60 mA 0 < CIcc < 60 mA Max. charge 20 nA.s CVCC Card Supply Voltage during spike on Icc 4.5 5.5 Max. duration 400 ns Max. variation CICC 100 mA TOFF CVcc to 0 750 s Cload=10F, Lload=10H Vcard = CVcc to 0.4V Cload=10F, Lload=10H TON 0 to CVcc 750 s Vcard = 0V to CVcc With Boost at 60% Test Conditions
Card VCC 3V Power Supply (for IEC7816-3 Class B cards)
Symbol Vcc CICC_ovf CVCC Parameter Power Supply Card Supply Current overflow Card Supply Voltage Ripple on Vcard 2.76 Min 3.6 100 3.24 200 Typ Max 5.5 Unit V mA V mV CICC = 60 mA 0 < CICC < 60 mA Maxi. charge 10nA.s CVCC Card Supply Voltage during spike on Icc 2.7 3.3 V Max. duration 400 ns Max. variation CICC 50mA TOFF CVcc to 0 750 s Cload=10F, Lload=10H Vcard = CVcc to 0.4V Cload=10F, Lload=10H TON 0 to CVcc 750 s Vcard = 0V to CVcc With Boost at 60% Test Conditions
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Card VCC 1.8V Power Supply (for IEC7816-3 Class C cards)
Symbol Vcc CICC_ovf CVCC TOFF Parameter Power Supply Card Supply Current overflow Card Supply Voltage CVcc to 0 1.68 Min 3.6 100 1.92 750 Typ Max 5.5 Unit V mA V s CICC = 30 mA Cload=10F, Lload=10H Vcard = CVcc to 0.4V Cload=10F, Lload=10H TON 0 to CVcc 750 s Vcard = 0V to CVcc With Boost at 60% Test Conditions
Notes:
1. Test conditions, Capacitor 10 F, Inductance 10 H. 2. Ceramic X7R, SMD type capacitor with minimum ESR or 250 m is mandatory
Smart Card CCLK, DC parameters
Symbol VOL IOL Parameter Output Low Voltage Output Low Current 0.7 CVCC VOH Output High Voltage 0.7 CVCC 0.7 CVCC CVCC - 0.5 IOH tR tF Output High Current Min 0(1) 0(1) Typ Max 0.2xVCC 0.4 15 CVCC CVCC CVCC CVCC 15 16 Rise and Fall delays 22.5 50 Voltage Stability -0.25 CVCC-0.5 Frequency variation Cycle ratio 45% 0.4 CVCC CVCC + 0.25 1% 55% ns mA V V V V mA CIN=30pF (5V) CIN=30pF (3V) CIN=30pF (1.8V) Low level High level IOH = 20 A (1.8V) IOH = 20 A (3V) IOH = 20 A (5V) IOH = 50 A (5V) Unit V Test Conditions IOL = 20 (1.8V, 3V) IOL= 50 A (5V)
V
Notes:
1. The voltage on CLK should remain between -0.3V and VCC+0.3V during dynamic operation.
Smart Card CIO, DC Parameters
Symbol VIL IIL VIH IIH VOL Parameter Input Low Voltage Input Low Current Input High Voltage Input High Current 0.7 CVCC Min 0(1) 0(1) Typ Max 0.5 0.15 CVCC 500 CVCC -20 / +20 0.4 Output Low Voltage 0(1) 0.4 0.3 V Unit V A V A IOL = 1mA (5V) IOL = 1mA (3V) IOL = 1mA (1.8V) IIH = -20 A Test Conditions IIL= 500 A IIL = 20 A
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Smart Card CIO, DC Parameters
Symbol IOL VOH IOH Parameter Output Low Current Output High Voltage Output High Current Voltage Stability tR tF Rise and Fall delays -0.25 0.8 CVCC 0.8 CVCC 0.7 CVCC Min Typ Max 15 CVCC (1) 15 0.4 CVCC + 0.25 0.8 s Unit mA V mA V Low level High level CIN=30pF. IOH = 20 A (5V) IOH = 20 A (3V, 1.8V) Test Conditions
Note:
1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation.
Smart Card RST, CC4, CC8, DC Parameters
Symbol VOL IOL VOH IOH tR tF Parameter Output Low Voltage Output Low Current Output High Voltage Output High Current Rise and Fall delays Voltage Stability -0.25 CVCC-0.5 CVCC - 0.5 0.8 x VCC Min 0(1) 0(1) Typ Max 0.12 x VCC 0.4 15 CVCC CVCC (1) 15 0.8 0.4 x CVCC CVCC + 0.25 Unit V mA V mA s CIN=30 pF Low level High level IOH = 50 IOH = 20 Test Conditions IOL = 20 IOL= 50
Note:
1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation.
Card Presence (P1.2) DC Parameters
Symbol IOL1 Parameter CPRES weak pull-up output current Min 3 Typ 10 Max 25 Unit A Test Conditions P1.2=1, short to VSS Pull-up enabled
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USB Interface
Figure 113. USB Interface
Symbol Parameter USB Reference Voltage Input High Voltage for D+ and D- (driven) Input High Voltage for D+ and D- (floating) Input Low Voltage for D+ and DOutput High Voltage for D+ and DOutput Low Voltage for D+ and D2.8 0.0 Min 3.0 2.0 2.7 Typ(5) Max 3.6 4.0 3.6 0.8 3.6 0.3 Unit V V V V V V
VREF
VIH VIHZ VIL VOH VOL
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AC Parameters
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40C to +85C; VSS = 0V; VCC = 3.6V to 5.5V ; FCK_CPU = 0 to 24 MHz. (Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs = 60 pF.) Table and Table 118 give the description of each AC symbols. Table 117 and Table 120 give for each range the AC parameter. Table 115, Table 117 and Table 119 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value and use this value in the formula. Example: TLLIV and 20 MHz, Standard clock. x = 30 ns T = 50 ns TCCIV = 4T - x = 170 ns External Program Memory Characteristics
Table 114. Symbol Description
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Parameter CPU clock period (FCK_CPU) ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float
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Table 115. AC Parameters for a Variable Clock
Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard clock 2T - x T-x T-x 4T - x T-x 3T - x 3T - x x T-x 5T - x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x X parameter 15 20 20 35 15 25 45 0 15 45 10 Units ns ns ns ns ns ns ns ns ns ns ns
External Program Memory Read Cycle
12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH TLLAX TAVLL INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXAV TPXIZ A0-A7 INSTR IN
PSEN PORT 0
TPXIX INSTR IN
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External Data Memory Characteristics Table 116. Symbol Description
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high
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Table 117. AC Parameters for a Variable Clock
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T - x 6T - x 5T - x x 2T - x 8T - x 9T - x 3T - x 3T + x 4T - x T-x 7T-x T-x x T-x T-x X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T - x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x X parameter 20 20 25 0 20 40 60 25 25 25 15 25 10 0 15 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(warning x value differ from AT89C51RD2) External Data Memory Write Cycle
ALE TWHLH
PSEN
TLLWL
TWLWH
WR TLLAX PORT 0 A0-A7 ADDRESS OR SFR-P2 TAVWL ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX
PORT 2
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External Data Memory Read Cycle
TWHLH
ALE
TLLDV
PSEN
TLLWL
TRLRH TRHDZ TRHDX DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2
RD TLLAX PORT 0 ADDRESS OR SFR-P2 A0-A7 TAVWL
TAVDV
PORT 2
Serial Port Timing - Shift Register Mode
Table 118. Symbol Description (F = 40 MHz)
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Table 119. AC Parameters for a Variable Clock
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12T 10T - x 2T - x x 10T - x X2 Clock 6T 5T-x T-x x 5 T- x 50 20 0 133 X parameter Units ns ns ns ns ns
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Shift Register Timing Waveform
INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI TXHQX 0 TXHDV
VALID VALID
0
1
2
3
4
5
6
7
8
1
2 TXHDX
VALID
3
4
5
6
7 SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
External Clock Drive Characteristics (XTAL1)
Table 120. AC Parameters
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Parameter Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Min 125 5 5 5 5 60 Max Units ns ns ns ns ns %
External Clock Drive Waveforms
VCC-0.5V 0.45V
0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCHCX TCLCH
AC Testing Input/Output Waveforms
INPUT/OUTPUT
VCC -0.5V 0.45V
0.2 VCC + 0.9 0.2 VCC - 0.1
AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurement are made at VIH min for a logic "1" and VIL max for a logic "0".
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Float Waveforms
FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
STATE4 P1 P2 STATE5 P1 P2 STATE6 P1 P2 STATE1 P1 P2 STATE2 P1 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2
INTERNAL
CLOCK XTAL2 ALE
EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION
PCL OUT
DATA SAMPLED FLOAT
PCL OUT
P2 (EXT) READ CYCLE RD
INDICATES ADDRESS TRANSITIONS
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
P0
P2 WRITE CYCLE
DPL OR Rt OUT
DATA SAMPLED FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WR P0
P2 PORT OPERATION MOV PORT SRC MOV DEST P0 OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED DPL OR Rt OUT DATA OUT
PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED
MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0)
RXD SAMPLED
RXD SAMPLED
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This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. USB Interface Rise Time 90% VCRS 10% Differential Data Lines tF 10% VLmax 90% Fall Time VHmin
tR
Symbol tR tF tFDRATE VCRS tDJ1 tDJ2 tJR1 tJR2
Parameter Rise Time Fall Time Full-speed Data Rate Crossover Voltage Source Jitter Total to next transaction Source Jitter Total for paired transactions Receiver Jitter to next transaction Receiver Jitter for paired transactions
Min 4 4 11.9700 1.3 -3.5 -4 -18.5 -9
Typ(5)
Max 20 20 12.0300 2.0 3.5 4 18.5 9
Unit ns ns Mb/s V ns ns ns ns
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Packaging Information
Ordering Information
Standard Part Number AT83C5122xxx-RDTIM AT83C5122xxx-RDRIM AT83C5122xxx-SISIM AT83C5122xxx-SIRIM AT83C5122xxx-PSVIM AT83C5122xxx-PSFIM Lead free/ RoHS Part Number AT83C5122xxx-RDTUM AT83C5122xxx-RDRUM AT83C5122xxx-SISUM AT83C5122xxx-SURIM AT83C5122xxx-PSTUM AT83C5122xxx-PSRUM Memory Size (bytes) 32K ROM 32K ROM 32K ROM 32K ROM 32K ROM 32K ROM Supply Voltage (V) 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 Temperature Max Frequency Range (MHz) Industrial Industrial Industrial Industrial Industrial Industrial 48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1 Package VQFP64 VQFP64 PLCC28 PLCC28 QFN64 QFN64 Packing Tray Tape & Reel Stick Tape & Reel Tray & Dry Pack Tape & Reel & Dry Pack
AT83EC5122xxx-RDVIM
AT83EC5122xxx-RDTUM
30K ROM + 512 Bytes EEPROM 30K ROM + 512 Bytes EEPROM 30K ROM + 512 Bytes EEPROM 30K ROM + 512 Bytes EEPROM
3.6 - 5.5
Industrial
48 MHz / X1
VQFP64
Tray & Dry pack
AT83EC5122xxx-RDFIM
AT83EC5122xxxRDRUM
3.6 - 5.5
Industrial
48 MHz / X1
VQFP64
Tape & Reel & Dry pack Tray & Dry Pack Tape & Reel & Dry Pack
AT83EC5122xxx-PSVIM
AT83EC5122xxx-PSTUM
3.6 - 5.5
Industrial
48 MHz / X1
QFN64
AT83EC5122xxx-PSFIM
AT83EC5122xxx-PSRUM
3.6 - 5.5
Industrial
48 MHz / X1
QFN64
AT85C5122D-RDTIM AT85C5122D-RDRIM AT85C5122D-SISIM AT85C5122D-SIRIM
AT85C5122D-RDTUM AT85C5122D-RDRUM AT85C5122D-SISUM AT85C5122D-SIRUM
32K CRAM 32K CRAM 32K CRAM 32K CRAM
3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5
Industrial Industrial Industrial Industrial
48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1
VQFP64 VQFP64 PLCC28 PLCC28
Tray Tape & Reel Stick Tape & Reel
AT89C5122D-RDVIM(1) AT89C5122D-RDFIM(1)
AT89C5122D-RDTUM AT89C5122D-RDRUM
32K FLASH 32K FLASH
3.6 - 5.5 3.6 - 5.5
Industrial Industrial
48 MHz / X1 48 MHz / X1
VQFP64 VQFP64
Tray & Dry pack Tape & Reel & Dry pack Tray & Dry Pack Tape & Reel & Dry Pack
AT89C5122D-PSVIM AT89C5122D-PSFIM
AT89C5122D-PSTUM AT89C5122D-PSRUM
32K FLASH 32K FLASH
3.6 - 5.5 3.6 - 5.5
Industrial Industrial
48 MHz / X1 48 MHz / X1
QFN64 QFN64
201
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Standard Part Number AT89C5122DS-RDVIM AT89C5122DS-RDFIM AT89C5122DS-PSVIM AT89C5122DS-PSFIM
Lead free/ RoHS Part Number AT89C5122DS-RDTUM AT89C5122DS-RDRUM AT89C5122D-PSTUM AT89C5122D-PSRUM
Memory Size (bytes) 32K FLASH 32K FLASH 32K FLASH 32K FLASH
Supply Voltage (V) 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5
Temperature Max Frequency Range (MHz) Industrial Industrial Industrial Industrial 48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1
Package VQFP64 VQFP64 QFN64 QFN64
Packing Tray & Dry Pack Tape & Reel & Dry Pack Tray & Dry Pack Tape & Reel & Dry Pack
AT83C5123xxx-RATIM AT83C5123xxx-RARIM AT83C5123xxx-SISIM AT83C5123xxx-SIRIM AT83C5123xxx-PUTIM AT83C5123xxx-PURIM
AT83C5123xxx-RATUM AT83C5123xxx-RARUM AT83C5123xxx-SISUM AT83C5123xxx-SIRUM AT83C5123xxx-PUTUM AT83C5123xxx-PURUM
30K ROM 30K ROM 30K ROM 30K ROM 30K ROM 30K ROM
3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5 3.6 - 5.5
Industrial Industrial Industrial Industrial Industrial Industrial
48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1 48 MHz / X1
VQFP32 VQFP32 PLCC28 PLCC28 QFN32 QFN32
Tray Tape & Reel Stick Tape & Reel Tray Tape & Reel
AT83EC5123xxx-RAVIM
AT83EC5123xxx-RATUM
30K ROM + 512 Bytes EEPROM 30K ROM + 512 Bytes EEPROM 30K ROM + 512 Bytes EEPROM 30K ROM + 512 Bytes EEPROM
3.6 - 5.5
Industrial
48 MHz / X1
VQFP32
Tray & Dry pack
AT83EC5123xxx-RAFIM
AT83EC5123xxx-RARUM
3.6 - 5.5
Industrial
48 MHz / X1
VQFP32
Tape & Reel & Dry pack Tray & Dry Pack Tape & Reel & Dry Pack
AT83EC5123xxx-PUVIM
AT83EC5123xxx-PUTUM
3.6 - 5.5
Industrial
48 MHz / X1
QFN32
AT83EC5123xxx-PUFIM
AT83EC5123xxx-PURUM
3.6 - 5.5
Industrial
48 MHz / X1
QFN32
Note:
1. Check avaibility with sales office
202
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Mechanical Dimensions
PLCC28 Package
203
4202D-SCR-06/05
VQFP64 Package
204
AT8xC5122/23
4202D-SCR-06/05
AT8xC5122/23
PLCC68 Package
205
4202D-SCR-06/05
VQFP32 Package
206
AT8xC5122/23
4202D-SCR-06/05
AT8xC5122/23
QFN32 Package
207
4202D-SCR-06/05
QFN64 Package
208
AT8xC5122/23
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AT8xC5122/23
Change Log
Changes from 4202A to 4202B
1. Product AT8xEC5122 added. 2. Products AT83C5123 and AT83EC5123 added.
Changes from 4202B to 4202C
1. All sections updated. 2. QFN64 and QFN32 packages added. 3. SCIB section : VCC must be higher than 4.0V when DC/DC is operated at 5V.
Changes from 4202C to 4202D
1. Product AT89C5122DS added (EA pin changed to VCC) 2. Typical applications section: external pull-up shown on CIO pin 3. Ports section : Detailed explanations on CIO, CC4, CC8 quasi-bidirectional ports 4. Ordering information section: AT89C5122DS part-numbers added
209
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AT8xC5122/23
Table of Contents
Features ................................................................................................. 1
Reference Documents .......................................................................................... 2 Product Description .............................................................................................. 3 AT8xC5122 Block Diagram .................................................................................. 5 AT83C5123 Block Diagram .................................................................................. 5
Pinout .................................................................................................... 6
High Pin Count Package Description.................................................................... 6 Low Pin Count Package Description .................................................................. 11 Pin Description.................................................................................................... 13
Typical Applications ........................................................................... 17
Recommended External components .................................................................17 USB Keyboard with Smart Card Reader using the AT8xC5122 and AT89C5122DS versions ............................................................................................................................. 18 USB Smart Card Reader using the AT83C5123 version.................................... 19
Memory Organization ......................................................................... 20
Program Memory Managament .......................................................................... 20 Data Memory Managament ................................................................................ 21 Dual Data Pointer Register (DDPTR) ................................................................. 22 Registers............................................................................................................. 24 AT8xC5122's CRAM and E2PROM versions ..................................................... 26 AT8xC5122's ROM version ................................................................................ 30 AT83C5123 version ............................................................................................ 32
Special Function Registers (SFR's) .................................................. 33
Introduction ......................................................................................................... AT8xC5122 Version............................................................................................ AT83C5123 Version ........................................................................................... SFR's Description ............................................................................................... 33 34 35 36
Clock Controller .................................................................................. 41
On-Chip Oscillator .............................................................................................. Phase Lock Loop (PLL) ...................................................................................... Clock Tree Architecture ...................................................................................... Registers............................................................................................................. 41 42 43 50
I/O Port Definition ............................................................................... 53
Port Configuration............................................................................................... 57 Registers............................................................................................................. 61
Smart Card Interface Block (SCIB) ................................................... 64
Block Diagram .................................................................................................... 65 210
4202D-SCR-06/05
Definitions ........................................................................................................... 65 Functional Description ........................................................................................ 67 Additional Features............................................................................................. 74 Alternate Card..................................................................................................... 78 Registers ............................................................................................................. 78 DC/DC Converter................................................................................................ 88
USB Controller .................................................................................... 95
Description.......................................................................................................... 96 Configuration ...................................................................................................... 99 Read/Write Data FIFO ...................................................................................... 102 Bulk / Interrupt Transactions............................................................................. 103 Control Transactions......................................................................................... 107 Isochronous Transactions................................................................................. 108 Miscellaneous ................................................................................................... 110 Suspend/Resume Management .......................................................................111 Detach Simulation............................................................................................. 114 USB Interrupt System ....................................................................................... 115 Registers........................................................................................................... 117
Serial I/O Port .................................................................................... 126
Framing Error Detection ................................................................................... Automatic Address Recognition........................................................................ Asynchronous Modes (Modes 1, 2 and 3) ........................................................ Modes 2 and 3 .................................................................................................. Registers........................................................................................................... 126 127 131 132 135
Serial Port Interface (SPI) ................................................................ 137
Features............................................................................................................ 137 Signal Description............................................................................................. 137 Functional Description ...................................................................................... 139
Timers/Counters ............................................................................... 147
Timer/Counter Operations ................................................................................ Timer 0.............................................................................................................. Timer 1.............................................................................................................. Registers........................................................................................................... 147 147 150 152
Keyboard Interface ........................................................................... 155
Introduction ....................................................................................................... 155 Description........................................................................................................ 155 Registers........................................................................................................... 156
Interrupt System ............................................................................... 159
Introduction ....................................................................................................... 159 Interrupt System Description ............................................................................ 159
211
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Registers........................................................................................................... 162 Interrupt Sources and Vectors .......................................................................... 171
Microcontroller Reset ....................................................................... 172
Introduction ....................................................................................................... Power On Reset (POR) .................................................................................... Power Fail Detector (PFD)................................................................................ Reset pin........................................................................................................... Watchdog Timer ............................................................................................... 172 173 173 175 177
Power Management .......................................................................... 180
Idle Mode .......................................................................................................... Power Down Mode ........................................................................................... Reduced EMI Mode .......................................................................................... USB Interface ................................................................................................... Smart Card Interface ........................................................................................ Keyboard Interface ........................................................................................... Watchdog Timer during Power-down and Idle Mode........................................ Registers........................................................................................................... 180 180 181 182 183 184 184 185
Electrical Characteristics ................................................................. 186
Absolute Maximum Ratings ..............................................................................186 DC Parameters .................................................................................................186 LED's ................................................................................................................188 Smart Card Interface ........................................................................................ 189 USB Interface ................................................................................................... 192 AC Parameters ................................................................................................. 193 Float Waveforms............................................................................................... 199
Packaging Information ..................................................................... 201
Ordering Information......................................................................................... 201 Mechanical Dimensions.................................................................................... 203
Change Log ....................................................................................... 209
Changes from 4202A to 4202B ........................................................................209 Changes from 4202B to 4202C ........................................................................209 Changes from 4202C to 4202D ........................................................................209
Table of Contents ............................................................................. 210
212
4202D-SCR-06/05
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